AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 49

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hop with Pin Sync
Just as
pins, A, B, C, and D, which are used for very accurate channe
synchronization. Each DDC channel can be programmed to
respond to any or all four SYNC pins.
Synchronization of hop with one of the external SYNC pins is
described as follows:
1.
2.
3.
4.
W
appropriate value (greater than 0 and less than 2 ).
Write the NCO Frequency Register(s), 0x85 and 0x86, to
the new desired frequency.
Set t
pin
Set the sync input select bits for each active channel. This is
done at Address 0x88:8–7. The truth table for these bits is
the same as for the start with pin sync, in Table 20.
in the start function, the AD6652 provides four SYNC
rite the NCO frequency hold-off counter(s) (0x84) to the
enable high at External Address 4.
he hop on pin sync bit high and the appropriate sync
16
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When the selected sync pin is sampled high by the AD6652
CLK, this enables the count-down of the NCO frequency
hold-off counter. The counter is clocked with the AD6652 CL
signal. When it reaches a count of 1, the new frequency is
loaded into the NCO. Each Pin Syn
trigger event f
External Address 4:6 is set to logic high. When high, only the
first sync signal is recognized and any others are disregarded
until First Sync Only is re
channels do not need to be p
frequency hop.
Note: Each channel has a redundant pin-sync control registe
Address 0x82. This register mimics the programming as set in
External Memory Address 4:6–4. The user can control the pin
sync function of
0x88:8–7 registers, if i
application.
The time fro
goes high to when the NCO begins processing data is equal to
the time period set up by the NCO frequency hold-off counter
(0x84) plus five master clock cycles.
m when the external signal on the SYNC input pin
or the hold-off counter unless First Sync Only,
a DDC channel by writing to the 0x82 and
t is advantageous to do so in the
set. Unlike the start function, the
laced in sleep mode to achieve a
c logic high initiates a new
AD6652
r at
K