AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 57

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN_SYNC CONTROL REGISTER
Exte
This is t
B
T
o
b
cha
co
m
pin-
desi
Bit 4
o
D
selec
and u
co
als
chan
B
or facilitates the routing of the extern
DDC channels. This bit enables any pi
selected by Bits 3–0 above to be routed to a 4-to-1 multiplexer
and ultimately chosen to be the channel’s pin-sync signal that
controls the Hop function. See Figure 53. Programming this bit
also programs the Channel Address Register 0x82 of each
channel.
Bit 6 is used to ignore repetitive
bit is clear, each PIN_SYNC restarts or frequency hops th
channel. If this bit is set, then only the first occurrence causes
the action to occur. Programming this bit als
Channel Address Register 0x82 of each channel.
Bit 7 is reserved; the bits should be written to Logic 0.
SLEEP CONTROL REGISTER
External Address 3
In addition to sleep mode control, this register also provides
access to th
Bits 3–0
bit is lo
ind
mi
of e
Bit 4 is reserved and should be written to Logic 0.
f the external pin syn inputs: A, B, C, and/or D. One pin can
e assigned to all channels, one pin can be assigned to one
r facili
its 3–0 of this register are the PIN SYNC_EN control bits.
hese bits can be writt
it 5 is the hop enable bit. Writing this bit to logic high enables
DC channels. This b enables any pin-sync signals that were
emory map, 0x88) as to which pin-sync signal is selected. A
nfigurable at the channel level (in the channel address register
ntrols the start function. See Figure 53. Programming this bit
o programs the Cha nel Address Register 0x82 of each
ng this bit als
icated channel enters a low-p
nnel, or any combination in between. This register is fully
ach channel.
red. See Figure 53.
sync signal can be
ted by Bits 3–0 ab
nel.
rnal Address 4
is the start enable
ltimately chosen
w, the ch nel operates n
tates the routin
he write-only
control
e output port control register’s memory map.
an
o p
the sleep
rograms the
PI
it
c
en t
ove, to be routed to a 4-to
n
to
used in addition to a soft
g
bit. Writing this bit to logic hig
N_SYNC control register.
of the external pin-sync sig
be the channel’s pin-sy
mode
o by the controller to select any or all
Cha
of the indicated chan
synchronization signals. If this
orm
ow
er sleep mode. Program-
nnel Address Register 0x82
ally. If the bit is high, the
al pin-sync signal to all the
n-sync signals that were
o programs the
-sync signal, if
nc signal that
-1 multiplexer
nal to all the
nel. If the
h enables
e
Rev. 0 | Page 57 of 76
Bit 5 allows access to the output control port registers. When
this bit
Howeve
port con
Externa
output c
address
Control Registers
Bit 6–7 e reserv
DATA
Externa
These r
respecti
to or les
triggers
indicate
internal
last. At t
indicate in A[9:0
directio Once th
must be
DR2 is only 4 bits wide. Data written to the upper 4 bits of this
register are ignored. Likewise, reading from this register
produces only 4 LSBs.
Figure 63 is a block diagram of the memory structure.
CHANNEL ADDRESS REGISTERS (CAR)
0x00–0x7F: Coefficient Memory (CMEM)
This register is the coefficient memory (CMEM) used by the
RCF. It is memory mapped as 128 words by 20 bits. A second
128 words of RAM can be acces
writing Bit 8 of the RCF control register high at Channel
Address 0xA4. The filter calculated always uses the same
coefficients for I and Q. By using memory from both of thes
128 blocks, a filter of up to 160 taps can be calculated. Multiple
filters can be loaded and selected with a single internal
the coefficient offset register at Channel Address 0xA3.
0x80: Channel Sleep Register
This register contains the sleep bit for the channel. It mimics the
programming of Bits 0–3 at External Address 3. External
Address 3 provides simultaneous sleep mode control f
DDC channels. The use
desired. Sle
high.
is low
ADDR
egisters fo
l Ad
ar
vely. Al
n.
s than 2 bits. When Extern
d in
d
r, w
regist
his po
ontr
an i
regi
trol r
the fi
l Addr
ep mode is selected when this bit is written logic
hen th
ntern
dress
sters,
ol po
the A
, the
egist
er m
rst d
int,
l in
ES
ess 2–0
0
al access to the AD
ed and should be written lo
rm the data registers DR2, DR1, and DR0,
6 (CAR) points to the me
rt registers instead o
channel address re
CR and CAR. Thu
External Address [0] DR0 must b
data is transferre
]. Reads are performed i
is bit is set high, it allows access to
ers. When this bit is set h
emory map. See
section.
ternal data-words have widths that are eq
e address is set, Externa
ata register read to initiate an
S REGISTER
r can overwrite the data in 0x80, if
sed via this same location by
S
Table 29 in the Output Port
d to the internal memory
al Address 0 is written to, it
6652 based on the address
s, during writes to the
gisters are accessed.
f the normal channel
l Address [0] DR0
n the opposite
igh, the value in
mory map for the
w.
internal access.
e written
AD6652
the output
or all four
access to
ual
e