AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 58

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
0x81: Soft_SYNC Register
This register is used to initiate software-generated SYNC events
through the microport. It mimics the programming of Bits 4
and 5 at External Address 5. If the hop bit is written high, th
the hop hold-off c
to count down. When the count reaches a v
channel’s NCO frequency accumu tor is l
from Channel Addresses 0x85 and 0x86. W
written high, the start hold-off counter is loaded with the value
at Address 0x83 and begins to count down. When the count
reaches a value of 1
and the channel is started.
0x82: Pin_SYNC Register
This register m
Address 4. Because t
Address 4 applies to all four chan
particular channel by o
programming provided
user does
Unlike the two bits in 0x81 above, setting
Start_En (Bits 1 and 0) of this register does not trigger anything.
These bits simply allow, or enable, an external synchronizing
signal to be routed to the channel’s start and/or hop multi-
plexers. Even though a signal has been enabled to reach the
multiplexer, it still needs to be selected. This job is accomplished
by Bits 8 and 7 of 0x88, as discussed below. The schem
diagram of Figure 53 is helpful in under
enabling and selection bits of the invo ed registers.
Bit 2 of 0x82 engages the first sync only function for the
channel. This bit is a copy of External Address 4, Bit 6, but can
not need to reprogram the elements of this register.
imics Bits 4, 5, and 6 of External Memory Map
ounter at Address 0x84 is loaded and begins
, the sleep bit in Address 0x80 is written low
he programming at External Memory
verwriting the data in 0x82.If the initial
by External Address 4 is satisfactory, the
A[9:8] FROM
BITS [1:0] OF
ADDRESS 7
EXTERNAL
ACR,
2
nels, the user can customize a
la
Figure 63.
*CHANNEL DECODER CAN BE
OVERR
lv
DECODER*
S 1
S 2
CHANNEL
standing the Pin_SYNC
the Hop_En or the
oaded with the data
ENB
hen the start bit is
alue of 1, the
IDDEN BY BROADCAST FEATURE.
Block Diagram of the AD6652 Inte
TO
D 1
D 4
CHANNEL 0
MEMORY MAP
CHANNEL 1
MEMORY M
CHAN
MEMORY MA
CHANNEL
MEMORY MAP
atic
NEL 3
en
Rev. 0 | Page 58 of 76
2
AP
P
A
R
E
CAR, EXTERNAL
XTERNAL ADDRESS 3
DR2, DR1, DR0,
EXTERNAL
ADDRESSES 2, 1, 0
CCESS TO OUTPUT CONTROL
EGISTERS, BIT 5, SLEEP REGISTER,
be overwritten to change the programming of a particular
channel. If this bit is clear, each PIN_SYNC restarts or rehop
the channel. If this bit is set, then only the first sync pulse causes
the action to occur.
0x83: Start Hold-Off Counter
The start hold-off counter is loaded with t
written to this address. When the Start function is triggered by
either a Soft_SYNC or Pin_SYNC, the hold-off counter begins
decrementing. When the count reaches a value of one, the
channel is brought out of sleep mode and begins processing
data. If the channel is already running, the phase of the filter(s)
adjusted such that multiple AD6652s can be synchronized.
A periodic pulse on the SYNC pin ca
adjust the timing of the filters with the r
sample clo
inf
wr
SY
do
0x84: Hop or Frequency Hold-Off Counter
The NCO frequency hold-off counter is loaded with the 16-bit
value written to this address upon receipt of either a Soft_SYNC
or Pin_SYNC. The counter begins counting, and when the
count reaches a value of 1, the 32-bit NCO frequency word is
updated with the values at 0x85 and 0x
hop or Hop_SYNC. Writing this register to a value of 1 causes
the NCO frequency to be updated immediately when the SYNC
comes into the channel. If it is written to a 0, then no Hop
occurs. NCO hops can be either phase-continuous or non-
phase-continuous, depending upon the state of Bit 3 of the
ADDRESS B
rnal Memory Maps and Controls
ADDRESS 6
20
DATA BUS
8
itten to Logic
NC pulse arr
es not respond to a SYNC pulse.
ormation ab
US
ck. S
ee the 0xA1 register description for
out f
ive
1, t
s. If it is written to Logic 0, then the counter
OUTPUT PORT
hen the start occurs immediately after the
INPUT PORT
ilter phase adjustment. If this register is
REGISTERS
REGISTERS
CONTROL
CONTROL
ENB
0x00
0x08
0x1E
n be used in this way to
86. This is known as a
esolution of the ADC
he 16-bit value
further
s
is