AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 46

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
CHANNEL/CHI
The AD6652 has been designed to easily synchronize two
common functions: Start and Hop. While the AGC stage can
also be synchronized, it is not accommo
soft-sync and pin-sync signals normally associated with
AD6652 synchronization. Start and Hop functions are describe
in detail in the followin
acco plished with the use of a shadow register and a hold-off
counter. See Figure 52 for a simplified schematic of the NCO
shad
understand basic operation. Triggering of the hold-off counter
can
Pin_Sync (via any of the four AD6652 SYNC pins A, B, C, and
D). igure 53 details how synchronization signals are managed
for a
SOFT SYNC
There are two types of synchronization stimuli to choose from:
Soft_Sync and Pin_Sync. The first method is initiated over the
microport or serial programming port using a software routine.
The second method relies on an external stimulus that is
attached to one of the four synchronization input pins (SYNC
A, B, C, and D). In both cases, a logic high triggers the synchro-
nization process. Both methods can be used simultaneously by
setting the appropriate qualifiers.
START
Start refers to the startup of an individual channel or chip, or
multiple chips. If a channel is not used, it should be placed in
sleep mode to reduce power dissipation. Following a hard reset
(low pulse on the AD6652 RESET pin), all channels are placed
in sleep mode. Channels can also be manually placed in sleep
PIN SYNC
F
occur with either a Soft_Sync (v
m
ow register and NCO frequency hold-off counter to
single receive processing channel.
FREQUENCY
INPUTS FROM
0x85 AND
0x86 NCO
FROM
PRELOAD
Figure 52. NCO Shadow Register and Hold-Off Counter
0x84
CLK
D31
ENB
D0
D15
D0
HOLD-OFF
COUNTER
P SYNCHRONIZATION
REGISTER
NCO HOP
SHADOW
g sections. The synchronization is
NCO
Q31
TC
Q0
32
ia the microport), or a
D0
D31
FREQUENCY
REGISTER
dated using the versatile
NCO
I0
FROM TC OF
START HOLD-OFF
COUNTER
Q31
Q0
READBACK
REGISTER
32
ACCUMULATOR
TO NCO
PHASE
Rev. 0 | Page 46 of 76
d
mode by writing to the register controlling the sleep function,
External Address 3:3–0.
Before and after a start command is received by one or more
channels, the following occurs:
1.
2.
Note that start does not affect the AGC hold-off counter. The
counter can be triggered only by setting the sync now bit or by
pin sync signals (see the Automatic Gain C
What happens if a Start_Sync pulse is received while the
channel is awake (actively processing data)? This can actually be
a very useful tool to dynamically adjust the RCF phase or
timing to allow synchronization of multiple AD6652 ICs. Refer
to the discussions of Registers 0x83 and 0xA1 in the Channel
Address Register (CAR) section for further explanation.
Start with No Sync
If no synchronization is needed to start multiple channels or
multiple AD6652s, use the following method to initialize the
device:
1.
2.
3.
Just before the start command is issued, while the channel i
in sleep mode, any or all control registers, including filter
coefficients, can be safely reprogrammed without crashin
the AD6652 or creating unwanted output.
When a Start_Sync pulse is received, it transfers the
contents of the channel’s start hold-off register, 0x83, to the
counter’s preload inputs and commences counting. When
the count reaches a value of one, the channel is awakened
and initialized with the information from each applicab
register for a proper channel startup. However, if t
preload va
channel remains dormant.
To program a channel, put it in sleep mode (bit high,
External Address 3:3–0), then load all appropriate control
and memory registers to set up the proper channel
configuration.
Load the start hold-off counter (0x83) with a 16-bit value
from 1 to 2
Set the channel’s sleep bit low (External Address 3:3–0).
Awakening from sleep involves an internally generated
start command that performs the same functions as a
software-generated sync pulse. This activates the channel
after the hold-off counter reaches a value of one with the
newly programmed or previous parameters.
lue is 0, this defeats the start function, and the
16
− 1.
ontrol section).
he start
le
g
s