AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 44

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
for averaging and decimating the update samples and taking
their square root to f
mode. In place of the request de
cl
essed by the second-or
operates the same way a
way, the truncation error is calculated and the AGC loop
operates to maintain a constant truncation error level.
Apart from Bit 4 of the AGC control words, the only register
setting changes compared to the desired signal level mode is
that the desired clipping level is stored in the AGC desired le
registers (0x0C, 0x15) instead of the request signal level (as in
desired signal level mode).
SYNCHRONIZATION
In i stances where the AGC output is connected to a Rake
recei
aver
average power for AGC error calculation and loop filtering. This
ext rnal signal synchronizes the AGC changes to the Rake
rece
chan
esti ation. The external synchronization signal is connected t
one or more of the pin sync pins (A, B, C, or D).
Pin
coun
the u
the u
chos
AGC B shares the pin synch that the user has assigned to DDC
processing Channel 2. Therefore, the user must attach the
external sync signal to the pin sync that will be assigned to
DDC Channel 2.
The hold-off counter register, 0x0B and 0x13 for AGC A
AGC B, respectively, must be programmed with a 16-bit
ipping level is subtracted, leaving an error term to be proc-
e
n
m
iver and makes sure that the AGC gain word does not
synchronization requires the use of an AGC hold-off
age-and-update section of th
en for DDC C
ver, a signal from the Rake receiver can synchronize t
ge over a symbol period and, therefore, mor
ter. The hold-off counter of AGC A shares the pin sync th
ser has assigned to DDC processing Channel 0. Therefor
ser must attach the external sync signal to the pin sync
hannel 0. Likewise, the hold-off counter of
ind rms samples, as in desired signal level
der loop filter. The rest of the loop
s the desired signal level mode. This
sired signal level, a desired
e AD6652 to update the
e accurate
and
he
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vel
e,
o
at
number that corresponds to the number of CLK cycles that will
be counted ( a known delay) before a new C
is updated. Writing a logic high to
triggers the AGC hold-off counter with a one-shot pulse every
time the pin is written high. Once triggered, the counter counts
down to a value of one and then causes a start of decimation for
a ne
Note
counter. Setting the hold-off count to one provides the smallest
dela
If the user chooses not to use pin sync signals, the user can use
the ync Now command through the microport. Each AGC
cont
0x12
decimation for a new up
characte
to a ne
by
fun
Ea
hold-off counter unless First Sync Only of the AGC’s control
register (Bit 1) is set to logic high. When high, only the first sync
signal is recognized and any others disregarded until First Sync
Only is reset.
Along with updating a new decimation value, the CIC filter
accumulator can be reset if the Init on Sync bit (Bit 2) of the
AGC control register is set. Init on Sync is triggered by either
sync signal, pin sync, or sync now.
Addresses 0x0A to 0x11 have b
AGC A, and Addresses 0x12 to 0x19 have been reserved for
configuring AGC B. The register specifications are detailed in
Table 29.
passes the AG hold-off coun
ch Pin Sync logic high initiates a new trigger event for the
ctions witho
S
w update sample.
y.
rol register has a sync now bit in Registers 0x0A:3 and
: Setting the hold-off count to zero disables t
:3 that, whe
w logic hi
ristic an
ut d
n written high, performs an immediate start of
C
d does n
gh
being writte
elay.
date sample. This bit has a one-shot
ot need
een reserved for configuring
n to
ter
to be reset in order
the proper pin sync pin
s and performs sync
it. Use of the sync now bit
IC decimated value
he hold-off
to respond