AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 33

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

NUMERICALLY CON
FREQUENCY TRANSLATION TO BASEBAND
This processing stage comprises a digital tuner consisting
two multipliers, I and Q, and a 32-bit complex numerically
contr lled oscillator (NCO). Each channel of the AD6652 has
an inde
oscillato
−CLK
mode. The worst-case spurious signal from the NCO is better
than −100 dBc for all output frequencies.
The NCO frequency programmed in Registers 0x85 and 0x
interpreted as a 32-bit un
equation to calculate th
where:
NCO_FREQ is a decimal number equal to the 32-bit binary
number to be programm
f is the desired NCO output frequency in Hz.
CLK is the AD6652 DDC master clock rate (in Hz).
NCO SHADOW REGISTER
the next number to be used by the active egister whenever that
function’s hold-off counter causes the active register to be
updated with the new value. Active registers are also updated
with the contents of a shadow register any time the channel is
brought out of sleep mode.
The NCO shadow register is updated during normal program
ming of the registers through the microport or serial input p
The active frequency register can receive update data on
the NCO shadow register. When software reads back an NCO
frequency, it is reading back the active frequency register and
not the shadow register.
NCO FREQUENCY HOLD-OFF REGIST
When the NCO frequency registers are written, data is actua
passed to a shadow register. Data can be moved to the active
register by one of two methods: when the channel comes out of
sleep mode or when a SYNC hop occurs. As a result of either
event, a count-down counter is loaded with an NCO frequen
hold-off value. The 16-bit unsigned integer counter (0x84
st
one, the new frequency value in the shadow register is written to
the active NCO frequency register.
A shadow register generally precedes an active register. It holds
arts counting down at the DDC CLK rate and, when it reaches
/2 and
NCO
o
pendent NCO. The NCO serves as a quadrature local
r capable of producing an NCO frequency between
+CLK
_
FREQ
/2 with a resolution of CLK/2
=
2
32
e NCO frequency:
ed at 0x85 and 0x86.
×
signed integer. Use the following
⎛
⎜
⎝
CLK
TROLLED OSCILLATOR
f
⎞
⎟
⎠
r
32
in the complex
ER
ly from
)
of
86 is
lly
ort.
Rev. 0 | Page 33 of 76
cy
’s
-
The NCO can be set up to update its frequency immediately
upon receipt of a HOP_SYNC or START_SYNC, with no
hold-off count, by setting the hold-off count value to 1. S
the hold-off count to zero prevents any frequen
PHAS OFFS T
Th
th
pr
co
of
sy
phas
NC
Use t
feat
basis.
Byp
To bypass the NCO of the AD6652, set Bit 0 of 0x88 high. When
the NCO is bypassed, down-con ersion is not performed, and
the AD6652 channel functions simply as a real filter on comp
data. This feature is useful for baseband sampling applications,
where the A input is connected to the I signal path within the
filter and the B input is connected to the Q signal path. Bypass
ing the NCO might be desired, if the
been converted to baseband in prior analog stages or by other
digital preprocessing.
Phase Dither
The AD6652 provides a phase dither option for improving the
spurious performance o
Bit 1 of Register 0x88, which causes discrete spurs due to phase
truncation in the NCO to be randomized. The energy from
these spurs is spread into th
dynamic range is increased at the expense of slight decreases in
the SNR. The choice of whether to use phase dither in a sy
depends ultimately on the system goals. If lower sp
desired at the expense of a slightly raised noise flo
dither should be employed. If the lowest noise floor is desired
and higher spurs can be tolerated or filtered by subsequen
stages, then phase dither is not needed.
Amplitude Di
Amplitude dither can also be used to improve spurious
performance of the NCO. To enable amplitude dither, set Bit 2
of 0x88, which causes amplitude quantization errors to be
randomized within the angular-to-Cartesian conversion stage
of the NCO. This option reduces spurs at the expense of a
slightly raised noise floor and slightly reduced SNR. Amplitude
dither and phase dither can be used together, separately, or not
at all.
e phas
eted as a 16-bit
nchro
rrespo
2π ra
e pha
ures
O C
ass
e dif
he
Th
E
dians.
nized to roduc
ONTR L REG TER
NCO
se offs
e accu
of the
nds to
ese fe
feren
con
Th
ces.
atu
et r
mu
NC
ther
O
no
E
p
is regi
res are described i the f
trol re
egister
unsign
lator o he NC
O, wh
offset
ster
gis
e o
f the NCO. To enable phase dither, set
ich
, an
f t
ed
IS
(0
ter loca d at 0x
utputs
x87) a
allows ultiple
intege
d a 0x
e noise floor and spurious free
are co rolled o a per c
v
dd
O. This 16-b
r. A 0x0000 in this reg
FF
wi
nt
te
m
n
s a pro
th con
FF cor
digitized signal has already
ollo
gra
stan
88
res
NC
n
to conf
it regis
wing
mmab
ponds
t and k own
Os to
cy u
or, then phase
urs are
sect
pdat
le o
ter
han
to
igu
AD6652
be
n
an offs
ions.
ister
ffset t
is inte
re the
nel
es.
etting
t
stem
o
lex
r-
et
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