AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 63

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

INPUT PORT CONTROL REGISTERS
The i
f
m
m
s
usin
lo
LIA,
To access the input port registers, the progra gain contro
shou
addr
0x00: Lower Threshold A
This w
m
eq
n
in
r
0x01: Upper Threshold A
This w
m
eq
n
or
0x02: Dwell Time A
T
the lo
inpu
leas
regi
exc
load
th
incr
wait
0x03: Ga
B
c
b
w
th
B
eat
eloaded an awaits the input to drop back t his level.
etting Bit 5 of External Address 3 (sleep regi
lear, then t
ormal chip peration, this starts the dwell time counter. If he
ormal chip peration, this causes the appro iate LI pin (LIA
een exceed . However, if this bit is set, the LI pin is low
his word sets the time that the input signal must be at or
it 4 determ es the polarity of LIA and LIA
it 3 = 0 (Re
hen active. his allows maximum flexibility hen using
cations ava lable. Response to these settings is directed to
put signal increases above this value, then t e counter is
ode of operation, up to four different signal paths can be
onitored with these registers. These features are accessed by
antissa. If the upper 10 bits of Input Port A are less than o
antissa. If t e upper 10 bits of Input Port A re greater th
e input is a or below the lower threshold. I
is function
ual to this alue, then the lower threshold
ual to this alue, then the upper threshold as been met.
LIA
ursion in
ures used p
t 1. If set
ster. Wh
eases ab
s for the
g the CAR (External Address 6) to address the eight
ed and
ess to th
t level d
LIA
ld be wr ten high. The CAR is then wri en with the
npu
wer th
) to become active.
ord is 10 bits wide and maps to the 10 MSB of the
ord is 10 bits wide and maps to the 10 MSB of the
, LIB, and LIB pins.
t po
in Range A Control Register
d
begins to count high speed clo
reshold before the LI pin i
en the lower thresh
ove the lower threshold, the
he
ed
etector to work, the dw
to the upper threshold
in
ser
e c
o
h
o
to 0, the LI function
i
it
v
v
t
signal to fall below the l
T
.
rt control registers ena
rimarily for level con
LI signal is high when the up r threshold has
orrect input port register.
ved).
old is met fol
s are disable
, the dwel
ell time m t be set to a
ble variou
trol. Dep
ow
s deac
er th
coun
ck
o t
tivat
pe
l tim
m
tt
ha
pr
low
res
. If this bit is
h
e
f th
ster) a
h
d. T
cy
a
ter is r
us
s i
ndin
w
s been met. I
h
cles as long
nput-re
ing an
e signal
old again.
ed. For the
his is a 20
e counter i
g on the
nd then
eloaded
late
belo
l bit
-bit
an o
d
In
t
as
r
n
the
t
s
and
Rev. 0 | Page 63 of 76
w
r
Bit 2–0 determines the internal latency of the gain detect
function. When the LIA, LIA
typically
this is prior to the A
A
a
p
0x04: Lo
This word
mantissa. If the upp
e
n
input sign
reloaded and aw
0x05: Upper Threshold B
This w rd is 10 bits wide and maps to the 10 MSB of the
m
e
n
or
0x06: Dwell Time B
This wor
t
i
least
register
excursion
lo
the input
increases above the lower threshold, the counter is relo
waits for t
0x0: G
Bit 4 determines th
clear, then the LI signal is hig
been exceeded.
when active. Th
this function.
B
B
f
t
t
t
register a
b e programmed.
he lower threshold before the LI
nput level detector to work, th
unction
ypically u
his is prio
he ADC a
llows the internal
qual to this valu
qual to th
rogrammed.
ormal chip o
ormal ch
it 3 = 0
it 2–0 d
DC and with th
antissa
aded and begins to count high speed clock cycles as long as
LIB ) to become active
1. If set to 0, the LI functions are disabled. This is a 20-bit
o
ain Range B Control Register
. When the lower threshold is met following an
. When the LIB, LIB
. If the upper 10 bits of Input Port B are greater than or
d sets the time that the input signal must be at or below
used to change an attenuator or gain stage. Because
(Reserved.
etermines the internal latency of the gain detect
llows the internal delay of the LIB, LIB
wer Threshold B
is at or below the lower threshold. If the signal
he signal to fall below the lower threshold again.
al increases above this value, then the counter is
ip operation, this causes the appropriate LI pin (LIB
into the upper threshold, the dwell time counter is
sed to change an attenuator or gain stage. Because
r to the ADC, there is a latency associated with
nd with the settling of the gain change. This
is 10 bits wide and maps to the 10 MSB of the
is value, then the upper threshold has been met. In
peration, this starts the dwell time counter. If the
However
is allows maximum flexibility when using
aits the input to drop back to this level.
e, then the lower threshold has been met. In
e settling of the gain change. This register
delay of the LIA, LIA
e polarity of LIB and LIB
er 10 bits of Input Port B are less than or
DC, there is a latency associated with the
, if this bit is set, the LI pin is low
pins are made active, they are
h when the upper threshold has
pins are made active, they are
e dwell time must be set to at
pin is deactivated. For the
signal to be
. If this bit is
signal to
AD6652
aded and