FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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2 – ProASIC3 nano DC and Switching Characteristics
General Specifications
The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing,
and hot-swap I/O capability. Refer to the
more information.
DC and switching characteristics for –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA
specifications. Some restrictions might be added and will be reflected in future revisions of this
document. The –F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2
is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
Parameter
VCC
DC core supply voltage
VJTAG
JTAG DC voltage
VPUMP
Programming voltage
VCCPLL
Analog power supply (PLL)
VCCI
DC I/O output buffer supply voltage
VI
I/O input voltage
1
T
Storage temperature
STG
1
T
Junction temperature
J
Notes:
1. For flash programming and retention maximum limits, refer to
limits, refer to
Table 2-2 on page
2-2.
2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in
"ProASIC3 nano Ordering Information" section on page III
Table 2-1
may cause permanent damage to the device.
Limits
–0.3 to 1.65
–0.3 to 3.75
–0.3 to 3.75
–0.3 to 1.65
–0.3 to 3.75
–0.3 V to 3.6 V
–65 to +150
+125
Table 2-3 on page
2-2, and for recommended operating
Table 2-4 on page
2-3.
R e v i s i o n 8
for
Units
V
V
V
V
V
V
°C
°C
2 -1