FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-73 • ProASIC3 nano CCC/PLL Specification
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay
Block
3,4
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
6
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay
1,2
1
Delay Range in Block: Programmable Delay
1,2
2
1,2
Delay Range in Block: Fixed Delay
VCO Output Peak-to-Peak Period Jitter F
0.75 MHz to 50MHz
50 MHz to 250 MHz
250 MHz to 350 MHz
Notes:
1. This delay is a function of voltage and temperature. See
2. T
= 25°C, V
= 1.5 V
J
CC
3. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to
4. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs.
5. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For
example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI =
3.3 , VQ/PQ/TQ type of packages, 20 pF load.
8. SSOs are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ± 200 ps of
each other.
Minimum
1.5
IN_CCC
0.75
OUT_CCC
1,2
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
48.5
1.25
0.025
5
Max Peak-to-Peak Jitter Data
CCC_OUT
SSO ≤ 2
0.50%
1.00%
2.50%
Table 2-6 on page 2-5
for deratings.
Table 2-6 on page 2-5
for derating values.
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
Typical
Maximum
Units
350
MHz
350
MHz
200
ps
32
125
MHz
1.5
ns
300
µs
6.0
ms
1.6
ns
0.8
ns
51.5
%
15.65
ns
15.65
ns
2.2
ns
5,7,8
SSO ≤ 4
SSO ≤ 8
SSO ≤ 16
0.50%
0.70%
1.00%
3.00%
5.00%
9.00%
4.00%
6.00%
12.00%
2- 57