FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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ProASIC3 nano DC and Switching Characteristics
Combinatorial Cells Contribution—P
P
= N
C-CELL
C-CELL
N
is the number of VersaTiles used as combinatorial modules in the design.
C-CELL
α
is the toggle rate of VersaTile outputs—guidelines are provided in
1
F
is the global clock signal frequency.
CLK
Routing Net Contribution—P
P
= (N
+ N
NET
S-CELL
N
is the number of VersaTiles used as sequential modules in the design.
S-CELL
N
is the number of VersaTiles used as combinatorial modules in the design.
C-CELL
α
is the toggle rate of VersaTile outputs—guidelines are provided in
1
F
is the global clock signal frequency.
CLK
I/O Input Buffer Contribution—P
P
= N
INPUTS
INPUTS
N
is the number of I/O input buffers used in the design.
INPUTS
α
is the I/O buffer toggle rate—guidelines are provided in
2
F
is the global clock signal frequency.
CLK
I/O Output Buffer Contribution—P
P
= N
OUTPUTS
OUTPUTS
N
is the number of I/O output buffers used in the design.
OUTPUTS
α
is the I/O buffer toggle rate—guidelines are provided in
2
β
is the I/O buffer enable rate—guidelines are provided in
1
F
is the global clock signal frequency.
CLK
RAM Contribution—P
P
= P
MEMORY
AC11
N
is the number of RAM blocks used in the design.
BLOCKS
F
is the memory read clock frequency.
READ-CLOCK
β
is the RAM enable rate for read operations.
2
F
is the memory write clock frequency.
WRITE-CLOCK
β
is the RAM enable rate for write operations—guidelines are provided in
3
PLL Contribution—P
P
= P
+ P
PLL
DC4
AC13
F
is the output clock frequency.
CLKOUT
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (P
2- 10
C-CELL
α
*
/ 2 * P
* F
1
AC7
CLK
NET
α
) *
/ 2 * P
* F
C-CELL
1
AC8
CLK
INPUTS
α
*
/ 2 * P
* F
2
AC9
CLK
OUTPUTS
α
β
*
/ 2 *
* P
* F
2
1
AC10
CLK
MEMORY
β
* N
* F
*
+ P
BLOCKS
READ-CLOCK
2
AC12
PLL
*F
CLKOUT
1
* F
AC14
CLKOUT
R e visio n 8
Table 2-12 on page
2-11.
Table 2-12 on page
2-11.
Table 2-12 on page
2-11.
Table 2-12 on page
2-11.
Table 2-13 on page
2-11.
β
* N
* F
*
BLOCK
WRITE-CLOCK
3
Table 2-13 on page
2-11.
product) to the total PLL contribution.