FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Timing Characteristics
Table 2-65 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: T
Combinatorial Cell
Equation
INV
Y = !A
AND2
Y = A · B
NAND2
Y = !(A · B)
OR2
Y = A + B
NOR2
Y = !(A + B)
XOR2
Y = A
B
MAJ3
Y = MAJ(A, B, C)
XOR3
Y = A
B
MUX2
Y = A !S + B S
AND3
Y = A · B · C
Note:
For specific junction temperature and voltage supply levels, refer to
derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the
Macro Library
Guide.
Data
D
Q
DFN1
CLK
Data
D
DFN1C1
CLK
CLR
Figure 2-21 • Sample of Sequential Cells
= 70°C, Worst-Case VCC = 1.425 V
J
Parameter
–2
–1
t
0.40
0.46
PD
t
0.47
0.54
PD
t
0.47
0.54
PD
t
0.49
0.55
PD
t
0.49
0.55
PD
t
0.74
0.84
PD
t
0.70
0.79
PD
C
t
0.87
1.00
PD
t
0.51
0.58
PD
t
0.56
0.64
PD
Table 2-6 on page 2-5
Fusion, IGLOO/e, and ProASIC3/E
Out
Data
D
Q
En
DFN1E1
CLK
PRE
Out
Data
Q
D
Q
En
DFI1E1P1
CLK
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
Std.
Units
0.54
ns
0.63
ns
0.63
ns
0.65
ns
0.65
ns
0.99
ns
0.93
ns
1.17
ns
0.68
ns
0.75
ns
for
Out
Out
2- 51