A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 65

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Timing Characteristics
Table 2-65 • Combinatorial Cell Propagation Delays
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the
Macro Library
Figure 2-21 • Sample of Sequential Cells
Combinatorial Cell
INV
AND2
NAND2
OR2
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Note:
For specific junction temperature and voltage supply levels, refer to
derating values.
Commercial-Case Conditions: T
Guide.
Data
Data
CLK
CLK
CLR
Y = MAJ(A, B, C)
Y = A
Y = A !S + B S
Y = A · B · C
Y = !(A + B)
Y = !(A · B)
D
Y = A
D
Equation
Y = A + B
Y = A · B
Y = !A
DFN1C1
DFN1
B
B
Q
Q
C
Out
R e v i s i o n 8
Out
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter
t
t
t
t
t
t
t
t
t
t
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Data
Data
CLK
CLK
PRE
En
En
0.40
0.47
0.47
0.49
0.49
0.74
0.70
0.87
0.51
0.56
–2
D
D
DFI1E1P1
DFN1E1
Fusion, IGLOO/e, and ProASIC3/E
0.46
0.54
0.54
0.55
0.55
0.84
0.79
1.00
0.58
0.64
Q
–1
Q
Table 2-6 on page 2-5
ProASIC3 nano Flash FPGAs
Out
Out
0.54
0.63
0.63
0.65
0.65
0.99
0.93
1.17
0.68
0.75
Std.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 51
for

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