FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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ProASIC3 nano DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
Equivalent
Software
Default
Drive
Drive
Strength
2
I/O Standard
Strength
Option
3.3 V LVTTL/
8 mA
8 mA
3.3 V
LVCMOS
3.3 V
100 µA
8 mA
LVCMOS
Wide Range
2.5 V
8 mA
8 mA
LVCMOS
1.8 V
4 mA
4 mA
LVCMOS
1.5 V
2 mA
2 mA
LVCMOS
Notes:
1. Currents are measured at 85°C junction temperature.
2. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
Table 2-15 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
1. Commercial range (–20°C < T
A
2. Industrial range (–40°C < T
< 85°C)
A
3. I
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
IL
4. I
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
IH
larger when operating outside recommended ranges.
2- 16
VIL
VIH
Slew
Min.
Max
Min.
Rate
V
V
V
High –0.3
0.8
2
High –0.3
0.8
2
High –0.3
0.7
1.7
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2
1
Commercial
3
I
I
IL
IH
µA
µA
10
10
10
10
10
10
10
10
10
10
< 70°C)
R e visio n 8
1
VOL
VOH
I
I
OL
OH
Max.
Min.
V
Max. V
V
mA mA
3.6
0.4
2.4
8
3.6
0.2
VCCI – 0.2 100
100
µA
µA
3.6
0.7
1.7
8
0.45
VCCI – 0.45 4
2
Industrial
4
3
4
I
I
IL
IH
µA
µA
15
15
15
15
15
15
15
15
15
15
1
8
8
4
2