A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 32

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ProASIC3 nano DC and Switching Characteristics
Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF)
STD Speed Grade, Commercial-Case Conditions: T
For A3PN060, A3PN125, and A3PN250
I/O Standard
3.3 V LVTTL /
8
8 mA
3.3 V LVCMOS
3.3 V LVCMOS
100 µA 8 mA
Wide Range
2.5 V LVCMOS
8
8 mA
1.8 V LVCMOS
4
4 mA
1.5 V LVCMOS
2
2 mA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to
Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF)
STD Speed Grade, Commercial-Case Conditions: T
For A3PN020, A3PN015, and A3PN010
I/O Standard
3.3 V LVTTL /
8
8 mA
3.3 V LVCMOS
3.3 V LVCMOS
100 µA 8 mA
Wide Range
2.5 V LVCMOS
8
8 mA
1.8 V LVCMOS
4
4 mA
1.5 V LVCMOS
2
2 mA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
3. For specific junction temperature and voltage supply levels, refer to
2- 18
= 70°C, Worst Case VCC = 1.425 V
J
High
35
0.60
4.57
0.04 1.13 1.52
High
35
0.60
6.78
0.04 1.57 2.18
High
35
0.60
4.94
0.04 1.43 1.63
High
35
0.60
6.53
0.04 1.35 1.90
High
35
0.60
7.86
0.04 1.56 2.14
Table 2-6 on page 2-5
= 70°C, Worst Case VCC = 1.425 V
J
High
10
0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14
High
10
0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35
High
10
0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98
High
10
0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89
High
10
0.60 3.76 0.04 1.56 2.14 0.43 3.74 3.76 2.66 2.83
Table 2-6 on page 2-5
R e visio n 8
0.43 4.64 3.92 2.60 3.14
0.43 6.78 5.72 3.72 4.35
0.43 4.71 4.94 2.60 2.98
0.43 5.53 6.53 2.62 2.89
0.43 6.45 7.86 2.66 2.83
for derating values.
for derating values.

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