FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Page 37/106

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Timing Characteristics
Table 2-29 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: T
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Speed
Strength
Grade
t
t
DOUT
DP
2 mA
Std.
0.60
9.70
–1
0.51
8.26
–2
0.45
7.25
4 mA
Std.
0.60
9.70
–1
0.51
8.26
–2
0.45
7.25
6 mA
Std.
0.60
6.90
–1
0.51
5.87
–2
0.45
5.15
8 mA
Std.
0.60
6.90
–1
0.51
5.87
–2
0.45
5.15
Note:
For specific junction temperature and voltage supply levels, refer to
Table 2-30 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: T
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Speed
Strength
Grade
t
t
DOUT
DP
2 mA
Std.
0.60
7.19
–1
0.51
6.12
–2
0.45
5.37
4 mA
Std.
0.60
7.19
–1
0.51
6.12
–2
0.45
5.37
6 mA
Std.
0.60
4.57
–1
0.51
3.89
–2
0.45
3.41
8 mA
Std.
0.60
4.57
–1
0.51
3.89
–2
0.45
3.41
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
J
t
t
t
t
t
DIN
PY
PYS
EOUT
ZL
0.04
1.13
1.52
0.43
9.88
0.04
0.96
1.29
0.36
8.40
0.03
0.84
1.13
0.32
7.37
0.04
1.13
1.52
0.43
9.88
0.04
0.96
1.29
0.36
8.40
0.03
0.84
1.13
0.32
7.37
0.04
1.13
1.52
0.43
7.01
0.04
0.96
1.29
0.36
5.97
0.03
0.84
1.13
0.32
5.24
0.04
1.13
1.52
0.43
7.01
0.04
0.96
1.29
0.36
5.97
0.03
0.84
1.13
0.32
5.24
Table 2-6 on page 2-5
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
J
t
t
t
t
t
DIN
PY
PYS
EOUT
ZL
0.04
1.13
1.52
0.43
7.32
0.04
0.96
1.29
0.36
6.22
0.03
0.84
1.13
0.32
5.46
0.04
1.13
1.52
0.43
7.32
0.04
0.96
1.29
0.36
6.22
0.03
0.84
1.13
0.32
5.46
0.04
1.13
1.52
0.43
4.64
0.04
0.96
1.29
0.36
3.95
0.03
0.84
1.13
0.32
3.47
0.04
1.13
1.52
0.43
4.64
0.04
0.96
1.29
0.36
3.95
0.03
0.84
1.13
0.32
3.47
Table 2-6 on page 2-5
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
t
t
t
Units
ZH
LZ
HZ
8.82
2.31
2.50
ns
7.50
1.96
2.13
ns
6.59
1.72
1.87
ns
8.82
2.31
2.50
ns
7.50
1.96
2.13
ns
6.59
1.72
1.87
ns
6.22
2.61
3.01
ns
5.29
2.22
2.56
ns
4.64
1.95
2.25
ns
6.22
2.61
3.01
ns
5.29
2.22
2.56
ns
4.64
1.95
2.25
ns
for derating values.
t
t
t
Units
ZH
LZ
HZ
6.40
2.30
2.62
ns
5.44
1.96
2.23
ns
4.78
1.72
1.96
ns
6.40
2.30
2.62
ns
5.44
1.96
2.23
ns
4.78
1.72
1.96
ns
3.92
2.60
3.14
ns
3.33
2.22
2.67
ns
2.93
1.95
2.34
ns
3.92
2.60
3.14
ns
3.33
2.22
2.67
ns
2.93
1.95
2.34
ns
for derating values.
2- 23

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