FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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ProASIC3 nano DC and Switching Characteristics
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Preset
Data
C
Enable
B
CLK
A
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
Figure 2-10 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2- 38
D
Data_out
PRE
Y
E
Core
D
Q
Array
DFN1E1P1
E
R e visio n 8
L
DOUT
F
PRE
D
Q
DFN1E1P1
G
E
EOUT
H
I
PRE
J
D
Q
DFN1E1P1
K
E
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered