MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 1090

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
18.3.7
There are two methods of accessing the PCI Express configuration header:
18.3.7.1
To access internal configuration space, software must rely on the PCI Express configuration access register
(PEX_CONFIG_ADDR/ PEX_CONFIG_DATA) mechanism. To access external configuration space,
software can either use configuration access registers or the outbound ATMU mechanism. For the
configuration access register method, a value must be written to the PEX_CONFIG_ADDR register that
specifies the PCI Express bus, the device on that bus, the function within the device, and the configuration
register in that device that should be accessed. The PCI Express controller’s bus number is obtained from
the PCI Express configuration header (type 1). Then either a write or a read to the PEX_CONFIG_DATA
register triggers the actual write or read cycle to the configuration space. Note that accesses to the
little-endian PCI Express configuration space must be properly formatted. See
Order for Configuration
Note that external configuration transactions should not be attempted until the link has successfully
trained. Software can poll the LTSSM state status register (PEX_LTSSM_STAT) to check the status of link
training before issuing external configuration requests.
18.3.7.1.1
There are two types of configuration transactions (Type 0 and Type 1) needed to support hierarchical
bridges.
18.3.7.1.2
Software can also program one of the outbound ATMU windows to perform a configuration access. This
is accomplished by programming the ReadTType or WriteTType field of the desired PEXOWAR to 0x2.
Software must only issue 4-byte or less access to the ATMU configuration window and the access cannot
18-42
•
•
•
•
•
•
PCI Express outbound ATMU window
PCI Express configuration access registers (PEX_CONFIG_ADDR/PEX_CONFIG_DATA)
If the bus number, and device number equal to the PCI Express controller’s bus number and device
number, and the function number is zero, then an internal PCI Express configuration cycle access
is performed.
If the bus number does not equal the PCI Express controller’s bus number, but does equal the
secondary bus number (from the type 1 header) and the device number is 0, then a Type 0
configuration transaction is sent to the PCI Express link.
If the bus number does not equal the PCI Express controller’s bus number, and does not equal the
secondary bus number (from the type 1 header), and the bus number is less than or equal to the
subordinate bus number (from the type 1 header), then a Type 1 configuration transaction is sent
to the PCI Express link.
If none of the above conditions occur, then the PCI Express controller returns all 1s for reads and
ignores writes.
PCI Express Configuration Space Access
RC Configuration Register Access
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Configuration Access Register Mechanism
Outbound ATMU Configuration Mechanism (RC-Only)
Transactions,” for more information.
Section 18.4.1.2.1, “Byte
Freescale Semiconductor