MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 45

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
6-1
Freescale Semiconductor
MPC8533E Block Diagram .................................................................................................... 1-2
Integrated Security Engine Functional Blocks...................................................................... 1-16
Processing Transactions Across the On-Chip Fabric............................................................ 1-21
Multifunction Router Application Enabled by local bus, PCI Express,
Multifunction Printer Application Enabled by Local Bus, PCI Express,
Security Appliance Enabled by SEC, local bus, PCI, and Ethernet...................................... 1-24
IP SAN Host Adapter enabled by local bus, PCI Express, and Ethernet.............................. 1-25
VoIP Aggregation Application Enabled by local bus and Ethernet ...................................... 1-26
Local Memory Map Example ................................................................................................. 2-2
Local Access IP Block Revision Register 1 (LAIPBRR1) ..................................................... 2-6
Local Access IP Block Revision Register 2 (LAIPBRR2) ..................................................... 2-6
Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7) ....................... 2-7
Local Access Window n Attributes Registers (LAWAR0–LAWAR7) ................................... 2-7
General Utilities Registers Mapping to Configuration, Control,
PIC Mapping to Configuration, Control, and Status Memory Block ................................... 2-13
Device-Specific Register Mapping to Configuration, Control,
MPC8533E Signal Groupings (1/3)........................................................................................ 3-2
MPC8533E Signal Groupings (2/3) (Continued).................................................................... 3-3
MPC8533E Signal Groupings (3/3) (Continued).................................................................... 3-4
Configuration, Control, and Status Register Base Address Register (CCSRBAR)................ 4-5
Alternate Configuration Base Address Register (ALTCBAR) ............................................... 4-6
Alternate Configuration Attribute Register (ALTCAR) ......................................................... 4-6
Boot Page Translation Register (BPTR) ................................................................................. 4-7
Power-On Reset Sequence .................................................................................................... 4-10
Clock Subsystem Block Diagram ......................................................................................... 4-22
RTC and Core Timer Facilities Clocking Options ................................................................ 4-24
e500 Core Complex Block Diagram ....................................................................................... 5-2
Vector and Floating-Point APUs............................................................................................. 5-5
Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 5-7
Three-Stage Load/Store Unit .................................................................................................. 5-8
Instruction Pipeline Flow ...................................................................................................... 5-14
GPR Issue Queue (GIQ) ....................................................................................................... 5-15
e500 Core Programming Model............................................................................................ 5-17
MMU Structure ..................................................................................................................... 5-23
Effective-to-Real Address Translation Flow......................................................................... 5-24
Effective-to-Real Address Translation Flow (e500v2) ......................................................... 5-25
Core Register Model ............................................................................................................... 6-2
PCI, and Ethernet ............................................................................................................. 1-22
PCI, and Ethernet ............................................................................................................. 1-23
and Status Memory Block ................................................................................................ 2-12
and Status Memory Block ................................................................................................ 2-14
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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