MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 228

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
6-12
32–36
39–44
Bits
37
38
45
46
47
48
49
50
51
52
53
Name
UCLE User-mode cache lock enable. Used to restrict user-mode cache-line locking by the operating system
UBLE In the e500, it is the user BTB lock enable bit.
SPE SPE enable. (e500-specific).
WE
ME
CE
EE
PR
—
—
—
—
—
Reserved, should be cleared.
0 Any cache lock instruction executed in user-mode takes a cache-locking DSI exception and sets either
1 Cache-locking instructions can be executed in user-mode and they do not take a DSI for cache-locking (they
0 If software attempts to execute an instruction that accesses the upper word of a GPR, the SPE unavailable
1 Software can execute the following instructions:
Reserved, should be cleared.
Wait state enable. Allows the core complex to signal a request for power management, according to the states
of HID0[DOZE], HID0[NAP], and HID0[SLEEP].
0 The processor is not in wait state and continues processing. No power management request is signaled to
1 The processor enters wait state by ceasing to execute instructions and entering low-power mode. Details of
Critical enable
0 Critical input and watchdog timer interrupts are disabled.
1 Critical input and watchdog timer interrupts are enabled.
Reserved, should be cleared.
External enable
0 External input, decrementer, fixed-interval timer, and performance monitor interrupts are disabled.
1 External input, decrementer, fixed-interval timer, and performance monitor interrupts are enabled.
User mode (problem state)
0 The processor is in supervisor mode, can execute any instruction, and can access any resource (for example,
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged
PR also affects memory access control
Reserved, should be cleared.
Machine check enable
0 Machine check interrupts are disabled.
1 Machine check interrupts are enabled.
Reserved, should be cleared.
0 User-mode execution of the BTB lock instructions is disabled; privileged instruction exception taken instead.
1 User-mode execution of the BTB lock instructions for user mode is enabled.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ESR[DLK] or ESR[ILK]. This allows the operating system to manage and track the locking/unlocking of cache
lines by user-mode tasks.
may still take a DSI for access violations though).
exception is taken.
These instructions include the SPE instructions, embedded double-precision, and single-precision vector
floating-point instructions. (That is, all instructions that access the upper half of the 64-bit GPRs.)
external logic.
how wait state is entered and exited and how the processor behaves in the wait state are
implementation-dependent. On the e500, MSR[WE] gates the DOZE, NAP, and SLEEP outputs from the core
complex; as a result, these outputs negate to the external power management logic on entry to the interrupt
and then return to their previous state on return from the interrupt. WE is cleared on entry to any interrupt and
restored to its previous state upon return.
GPRs, SPRs, and the MSR).
resource.
Table 6-6. MSR Field Descriptions
1
1
1
1
1
Description
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