MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 129

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

registers is given in the following sections. Note that the minimum size of a window is 4 Kbytes, so the
low order 12 bits of the base address cannot be specified.
2.2.3.1
Table 2-4
field descriptions, the following access definitions apply:
Freescale Semiconductor
Local Memory
Offset (Hex)
•
•
•
•
•
0x0_0BFC
0x0_0CA8
0x0_0CB0
0x0_0CC8
0x0_0CD0
0x0_0CE8
0x0_0CF0
0x0_0BF8
0x0_0C08
0x0_0C10
0x0_0C28
0x0_0C30
0x0_0C48
0x0_0C50
0x0_0C68
0x0_0C70
0x0_0C88
0x0_0C90
0x0_0D08
0x0_0D10
0x0_0D28
0x0_0D30
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
shows the memory map for the local access registers. In this table and in the register figures and
Local Access Register Memory Map
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
LAIPBRR1—Local access IP block revision register 1
LAIPBRR2—Local access IP block revision register 2
LAWBAR0—Local access window 0 base address register
LAWAR0—Local access window 0 attribute register
LAWBAR1—Local access window 1 base address register
LAWAR1—Local access window 1 attribute register
LAWBAR2—Local access window 2 base address register
LAWAR2—Local access window 2 attribute register
LAWBAR3—Local access window 3 base address register
LAWAR3—Local access window 3 attribute register
LAWBAR4—Local access window 4 base address register
LAWAR4—Local access window 4 attribute register
LAWBAR5—Local access window 5 base address register
LAWAR5—Local access window 5 attribute register
LAWBAR6—Local access window 6 base address register
LAWAR6—Local access window 6 attribute register
LAWBAR7—Local access window 7 base address register
LAWAR7—Local access window 7 attribute register
LAWBAR8—Local access window 8 base address register
LAWAR8—Local access window 8 attribute register
LAWBAR9—Local access window 9 base address register
LAWAR9—Local access window 9 attribute register
Table 2-4. Local Access Register Memory Map
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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Memory Map
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