MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 216

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Complex Overview
5-32
HID1
Implementation
PIR value
PVR value
SVR value
Alternate time
base
Table 5-8. Differences Between the e500 Core and the PowerQUICC III Core Implementation (continued)
Feature
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PLL_MODE. Set to 01
PLL_CFG. This PowerQUICC III device supports the following:
0001_00Ratio of 2:1
0001_01Ratio of 5:2 (2.5:1)
0001_10Ratio of 3:1
0001_11Ratio of 7:2 (3.5:1)
NEXEN, R1DPE, R2DPE, MPXTT, MSHARS, SSHAR, ATS, and MID are not implemented
On PowerQUICC III devices, ABE must be set to ensure that cache and TLB management instructions
operate properly on the L2 cache.
Please refer to the description of HID1[RFXE] in
Register 1 (HID1).”
If RFXE is 0, conditions that cause the assertion of core_fault_in cannot directly cause the e500 to generate
a machine check; however, PowerQUICC III devices must be configured to detect and enable such conditions.
The following describes how error bits should be configured:
Local bus controller parity errors. LTEDR[PARD] must be cleared and LTEIR[PARI] must be set to ensure that
an parity errors can generate an interrupt. See
(LTEDR),”
The PIR value is all zeros on PowerQUICC III devices.
The PVR reset value is 0x80 nn _ nnnn. See
PVR[VERSION] = 0x80 nn
PVR[REVISION] = 0x nnnn
The SVR reset value is 0x80 nn _ nnnn. See
The alternate time base defines a time base counter similar to the time base defined in architecture. It is
intended to be used for measuring time in implementation defined intervals. It differs from the defined Time
Base in that it is not writable and always counts up, wrapping when the 64-bit count overflows. It defines two
SPRs, ATBL (SPR 526) and ATBL (SPR 527).
• ECM mapping errors: EEER[LAEE] must be set. See
• L2 multiple-bit ECC errors: L2ERRDIS[MBECCDIS] must be cleared to ensure that error can be detected.
• DDR multiple-bit ECC errors. ERR_DISABLE[MBED] and ERR_INT_EN[MBEE] must be zero and
• PCI. The appropriate parity detect and master-abort bits in ERR_DR must be cleared and the
L2ERRINTEN[MBECCINTEN] must be set. See
DDR_SDRAM_CFG[ECC_EN] must be one to ensure that an interrupt is generated. See
“Register Descriptions.”
corresponding enable bits in ERR_EN must be set to ensure that an interrupt is generated.
and
Section 14.3.1.12, “Transfer Error Interrupt Enable Register (LTEIR).”
PowerQUICC III Implementation
Table 5-1
Table 5-1
Section 14.3.1.11, “Transfer Error Check Disable Register
Section 6.10.2, “Hardware Implementation-Dependent
Section 7.3.1.4, “L2 Error Registers.”
for specific values.
for specific values.
Section 8.2.1.6, “ECM Error Enable Register (EEER).”
Freescale Semiconductor
Section 9.4.1,