MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 861

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.6.1.5
This section describes the ten-bit interface (TBI) intended to be used between the PHYs and the eTSEC to
implement a standard SerDes interface for optical-fiber devices in 1000BASE-SX/LX applications.
Figure 15-121
module connection with a PHY. RBC0 and RBC1 are differential 62.5 MHz receive clocks. If not
connected to the TBI PHY, the Signal Detect (SDET) input must be tied high. This causes the eTSEC to
begin auto negotiation with the SERDES immediately upon the TBI module being enabled.
A TBI interface has 26 signals (GE_GTX_CLK125 included) for connecting to an Ethernet PHY, as
defined by IEEE 802.3z GMII and TBI standards.
Freescale Semiconductor
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’
connections in the system, assuming that each PHY has a different management address.
eTSEC
Ten-Bit Interface (TBI)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
depicts the basic components of the TBI including the signals required to establish eTSEC
Gigabit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
TBI Receive Clock 0 (TSEC n _RX_CLK)
TBI Receive Clock 1 (TSEC n _TX_CLK)
SIGNAL DETECT (TSEC n _RX_CRS)
Figure 15-121. eTSEC-TBI Connection
Transmit Data (TSEC n _TXD[9:0])
Receive Data (TSEC n _RXD[9:0])
Management Data Clock
Management Data I/O
1
1
(MDIO)
(MDC)
Enhanced Three-Speed Ethernet Controllers
Ethernet
Gigabit
PHY
Medium
15-131