MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 1143

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The fields of the PCI Express configuration ready register are described in
18.3.10.19 PME_To_Ack Timeout Register (RC-Mode Only)—0x590
The PCI Express PME_To_Ack timeout register, shown in
value for a PME_To_Ack message response in terms of PCI Express controller core clock cycles.
The fields of the PCI Express PME_To_Ack timeout register are described in
18.3.10.20 Secondary Status Interrupt Mask Register (RC-Mode Only)—0x5A0
The PCI Express secondary status interrupt mask register, shown in
sideband interrupt generation when error bits in the PCI Express secondary status register are set. See
Section 18.3.8.3.8, “PCI Express Secondary Status
interrupt generation due to secondary status errors is disabled.
Freescale Semiconductor
Offset 0x590 (RC-mode only)
Reset 1
31–22
31–1
21–0 PME_TO_ACK_
Bits
Bits
0
W
R
31
Figure 18-120. PCI Express PME_To_Ack Timeout Register (PEX_PME_TO_ACK_TOR)
CFG_READY
0
TIMEOUT
Name
Name
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
—
—
0
0
—
0
Reserved
After a PME_Turn_Off message is broadcast by the RC, the power management module waits
for the duration of the PME_To_Ack timeout interval to receive a PME_To_Ack message from the
downstream device. If the Ack message is not received within this interval, the power manager
indicates that it is safe to switch off power, since timeout has occurred.
The value is calculated as:
The recommended timeout duration is 1 msec to 10 msec to make sure that the downstream
devices get enough time to prepare for power-off condition.
Reserved
Configuration ready
1 The transaction layer will accept inbound configuration requests.
0 The transaction layer will respond to all inbound configuration requests with retry (CRS)
Note that the reset state of this bit is determined during POR.
Table 18-115. PEX_PME_TO_ACK_TOR Field Descriptions
0
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
Table 18-114. PEX_CFG_READY Field Descriptions
0
0
22 21
0
0
0
0
0
0
Register—0x1E,” for more information. By default,
1
0
Description
Description
Figure
PME_TO_ACK_TIMEOUT
0
0
0
18-120, is used to program the timeout
Figure
0
1
0
18-121, can be used to disable
Table
0
Table
PCI Express Interface Controller
0
18-114.
0
18-115.
1
0
Access: Mixed
1
0
0
18-95
0
0