MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 582

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.6
The controller within the SEC is responsible for overseeing the operations of the execution units (EUs),
the interface to the host processor, and the management of the channels. The controller interfaces to the
host via the master/slave bus interface and to the channels and EUs via internal buses. All transfers
between the host and the EUs are moderated by the controller. Some of the main functions of the controller
are as follows:
12.6.1
Assignment of an EU to a channel is done dynamically. The channel requests an EU, the controller checks
to see if the requested EU is available, and if it is, the controller grants the channel assignment of the EU.
If an EU is available for a channel when requested, the controller will assert the grant signal pertaining to
the request from the channel. The grant signal will remain asserted until the channel is done and releases
the EU.
In some cases, a channel may request two EUs. The channel will do this by first requesting the primary
EU, then requesting the secondary EU. Once the controller has granted both EUs, this channel is then
capable of requesting that the secondary EU snoop the bus. Snooping status is indicated in the MI and MO
bits of
In all cases, the controller assigns the primary EU to a requesting channel as the EUs become available.
The controller does not wait until both EUs are available before issuing any grants to a channel which is
requesting two EUs.
Since there are multiple channels in the SEC, they must arbitrate for access to execution units. To
accomplish this, the controller implements one arbiter for each EU and one arbiter for the internal system
bus. These are snapshot arbiters, which means they operate as follows:
To choose which request to grant within a given snapshot, the arbiters can use either a weighted
priority-based or round-robin scheme, depending on the values of CHN3_EU_PR_CNT and
CHN4_EU_PR_CNT in the master control register
12-104
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Table
(MDEU) EU is also requested if one has been reserved for snooping. The channel then asserts the
appropriate release output signal to notify the controller that the channel has finished with the
reserved EU(s). The channel then resets all the registers, clears the RESET bit and returns the
control state machine to the idle state.
Provide arbitration for bus access and control bus accesses
Control the internal bus accesses to the EUs
Provide arbitration for channels requesting EUs and assign EUs to channels
Monitor interrupts from channels and pass to host
Realign read and write data to the proper byte alignment
When there are requests, the arbiter records the set of requests waiting (that is, it takes a snapshot)
Then it satisfies those requests as the resource becomes available.
When all requests in the snapshot have been satisfied, the arbiter takes another snapshot.
Security Controller
Assignment of EUs to Channels
12-52.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(see
Section 12.6.5.7, “Master Control Register
Freescale Semiconductor