MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 782

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.3
The RXIC register enables and configures the operational parameters for interrupt coalescing associated
with received frames.
15-52
Offset eTSEC1:0x2_4310; eTSEC3:0x2_6310
Reset
16–23
Bits
13
14
15
24
25
26
27
28
29
30
31
W
R
ICEN ICCS —
0
QHLT5 RxBD queue 5 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT6 RxBD queue 6 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT7 RxBD queue 7 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
Name
RXF0 Receive frame event occurred on ring 0. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF1 Receive frame event occurred on ring 1. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF2 Receive frame event occurred on ring 2. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF3 Receive frame event occurred on ring 3. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF4 Receive frame event occurred on ring 4. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF5 Receive frame event occurred on ring 5. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF6 Receive frame event occurred on ring 6. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
RXF7 Receive frame event occurred on ring 7. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
—
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Interrupt Coalescing Register (RXIC)
not cause a QHLT5 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT6 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT7 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
Reserved
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
frame to this ring.
2
3
Figure 15-24
Table 15-27. RSTAT Field Descriptions (continued)
ICFT
Figure 15-24. RXIC Register Definition
describes the RXIC register.
10 11
—
All zeros
Description
15 16
ICTT
Freescale Semiconductor
Access: Read/Write
31