MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 83

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table
Number
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
18-33
18-34
18-35
18-36
18-37
18-38
18-39
18-40
18-41
18-42
18-43
18-44
18-45
18-46
18-47
18-48
18-49
18-50
18-51
18-52
18-53
18-54
18-55
18-56
18-57
Freescale Semiconductor
PCI Express Error Disable Register Field Descriptions ..................................................... 18-34
PCI Express Error Capture Status Register Field Descriptions .......................................... 18-36
PCI Express Error Capture Register 0 Field Descriptions
PCI Express Error Capture Register 0 Field Descriptions
PCI Express Error Capture Register 1 Field Descriptions
PCI Express Error Capture Register 1 Field Descriptions
PCI Express Error Capture Register 2 Field Descriptions
PCI Express Error Capture Register 2 Field Descriptions
PCI Express Error Capture Register 3 Field Descriptions
PEX Error Capture Register 3 Field Descriptions
PCI Express Vendor ID Register Field Description............................................................ 18-44
PCI Express Device ID Register Field Description ............................................................ 18-44
PCI Express Command Register Field Descriptions .......................................................... 18-45
PCI Express Status Register Field Descriptions ................................................................. 18-46
PCI Express Revision ID Register Field Descriptions........................................................ 18-47
PCI Express Class Code Register Field Descriptions ......................................................... 18-48
PCI Express Bus Cache Line Size Register Field Descriptions.......................................... 18-48
PCI Express Bus Latency Timer Register Field Descriptions ............................................ 18-49
PCI Express Bus Latency Timer Register Field Descriptions ............................................ 18-49
PEXCSRBAR Field Descriptions ....................................................................................... 18-51
32-Bit Memory Base Address Register (BAR1) Field Descriptions .................................. 18-51
64-Bit Low Memory Base Address Register Field Descriptions........................................ 18-52
Bit Setting for 64-Bit High Memory Base Address Register.............................................. 18-52
PCI Express Subsystem Vendor ID Register Field Description ......................................... 18-53
PCI Express Subsystem ID Register Field Description ...................................................... 18-53
Capabilities Pointer Register Field Description.................................................................. 18-54
PCI Express Interrupt Line Register Field Description ...................................................... 18-54
PCI Express Interrupt Pin Register Field Description ........................................................ 18-55
PCI Express Maximum Grant Register Field Description.................................................. 18-55
PCI Express Maximum Latency Register Field Description .............................................. 18-56
PEXCSRBAR Field Descriptions ....................................................................................... 18-57
PCI Express Primary Bus Number Register Field Description .......................................... 18-57
PCI Express Secondary Bus Number Register Field Description ...................................... 18-58
Internal Source, Outbound Transaction.......................................................................... 18-37
External Source, Inbound Transaction ........................................................................... 18-37
Internal Source, Outbound Transaction.......................................................................... 18-38
External Source, Inbound Transaction ........................................................................... 18-39
Internal Source, Outbound Transaction.......................................................................... 18-40
External Source, Inbound Transaction ........................................................................... 18-40
Internal Source, Outbound Transaction.......................................................................... 18-41
External Source, Inbound Transaction ........................................................................... 18-41
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Tables
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Number
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