MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 661

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.4.2.2.4
The timing of LOE is affected only by TRLX. It always asserts and negates on the rising edge of the bus
clock. LOE asserts either on the rising edge of the bus clock after LCSn is asserted or coinciding with
LCSn (if XACS = 1 and ACS = 10 or 11). Accordingly, assertion of LOE can be delayed (along with the
assertion of LCSn) by programming TRLX = 1. LOE negates on the rising clock edge coinciding with
LCSn negation
14.4.2.2.5
Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose
some combination of ORn[TRLX,EHTR]. Any access following a read access to the slower memory bank
is delayed by the number of clock cycles specified by the configuration of ORn[TRLX,EHTR], as
described in
turnaround cycle. The final bus turnaround cycle is automatically inserted by the LBC for reads, regardless
of the setting of ORn[EHTR].
timing examples.
Freescale Semiconductor
LBCTL
LWE n
LCLK
LALE
LCS n
LOE
LAD
Section 14.3.1.2.2, “Option Registers (ORn)—GPCM Mode,”
TA
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
A
Output Enable (LOE) Timing
Extended Hold Time on Read Accesses
Address
(XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1)
Figure
Figure 14-29. GPCM Relaxed Timing Write
14-30,
SCY = 1, TRLX = 1
Figure
Latched Address
Write Data
14-31, and
CSNT = 1
Figure 14-32
in addition to any existing bus
present various GPCM
Local Bus Controller
14-43