MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 872

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.6.3.2
Before issuing a soft-reset to and/or reconfiguring the MAC with new parameters, the user must properly
shutdown the DMA and make sure it is in an idle state for the entire duration. User must gracefully stop
the DMA by setting both GRS and GTS bits in the DMACTRL register, then wait for both GRSC and
GTSC bits to be set in the IEVENT register before resetting the MAC or changing parameters. Both GRS
and GTS bits must be cleared before re-enabling the MAC to resume the DMA.
During the MAC configuration, if a new set of Tx buffer descriptors will be used, the user must load the
pointers into the TBASE registers. Likewise if a new set of Rx buffer descriptors will be used, the RBASE
registers must be written with new pointers.
Following is a procedure to gracefully reset and reconfigure the MAC:
15-142
2. For the transmission of Ethernet frames, TxBDs must first be built in memory, linked together as
3. Likewise, for the reception of Ethernet frames, the receive queue (or queues) must be ready, with
4. Clearing DMACTRL[GTS] triggers the transmission of frame data if the transmitter had been
1. Set GRS/GTS bits in DMACTRL register
2. Poll GRSC/GTSC bits in IEVENT register until both are set
3. Set SOFT_RESET bit in MACCFG1 register (Note that SOFT_RESET must remain set for at least
4. Clear SOFT_RESET bit in MACCFG1 register
5. Load TDBPH, TBASEH, TBASE0–TBASE7 with new Tx BD pointers
6. Load RDBPH, RBASEH, RBASE0–RBASE7 with new Rx BD pointers
7. Setup other MAC registers (MACCFG2, MAXFRM, etc.)
8. Setup group address hash table (GADDR0–GADDR15) if address filtering is required
9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) if filing to multiple RxBD rings
10. Setup WWR, WOP, TOD bits in DMACTRL register
11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set
12. Enable receive queues in RQUEUE, and optionally set TOE functionality in RCTRL.
13. Clear THLT and TXF bits in TSTAT register by writing 1 to them
a ring, and pointed to by the TBASEn registers. A minimum of two buffer descriptors per ring is
required, unless the ring is disabled. Setting the ring to a size of one causes the same frame to be
transmitted twice. If TCP/IP off-load is to be enabled, the TxBD[TOE] bit must be set for each
frame.
its RxBD pointed to by the RBASEn registers. If TCP/IP off-load is to be enabled,
RCTRL[PRSDEP] must be set to the required off-load level. Both transmit and receive can be
gracefully stopped after transmission and reception begins.
previously stopped. The DMACTRL[GRS] must be cleared if the receiver had been previously
stopped. Refer to the DMACTRL register section, and
Descriptors,”
3 TX clocks before proceeding.)
is required
in TCTRL.
Soft Reset and Reconfiguring Procedure
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
for more information.
Section 15.6.7.1, “Data Buffer
Freescale Semiconductor