MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 316

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

e500 Coherency Module
Table 8-5
8.2.1.5
The ECM error detect register (EEDR) is shown in
Table 8-6
8-6
Offset 0x0_1E00
Reset
16–23
24–31
8–15
1–30
Bits
Bits
0–7
31
W
R MULT_ERR
0
describes EIPBRR2 fields.
describes EEDR fields.
MULT_ERR Multiple error. Indicates the occurrence of multiple errors of the same type. Write 1 to clear.
w1c
Name
IP_CFG
0
IP_INT
LAE
Name
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
ECM Error Detect Register (EEDR)
—
—
1
0 Multiple errors of the same type were not detected.
1 Multiple errors of the same type were detected.
Reserved
Local access error. Write 1 to clear. Two cases can generate LAEs:
0 Local access error has not occurred.
1 Local access error occurred.
• Transaction does not map to any target. In this case the ECM injects read responses (with the
• Source and target IDs indicate that an OCN port initiated a transaction that targets an OCN
Reserved
IP block integration options
Reserved
IP block configuration options
corrupt attribute set) and write data is dropped. Note that a read that attempts to access an
unmapped target causes the assertion of core_fault_in , which causes the core to generate a
machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and
this error occurs, EEER[LAEE] must be set to ensure that an interrupt is generated. For more
information, see
port. This loopback behavior can result from programming errors where inbound ATMU
window targets are inconsistent with targets configured in the local access windows for a given
address range. For this type of LAE, the dispatch (to OCN target in this case) is not screened
off; the LAE error is reported, but the transaction is still sent to its OCN target.
Figure 8-6. ECM Error Detect Register (EEDR)
Table 8-5. EIPBRR2 Field Descriptions
Table 8-6. EEDR Field Descriptions
Section 6.10.2, “Hardware Implementation-Dependent Register 1
Figure
All zeros
Description
Description
—
8-6.
Freescale Semiconductor
(HID1).”
Access: w1c
30
LAE
w1c
31