MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 1249

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

21.4.2
The DDR interface has two debug modes distinguished by which pins drive the debug information. In one
mode, debug information (source ID, data valid) is multiplexed onto the ECC pins; the other mode uses
the debug pins.
21.4.2.1
If MSRCID0 is high when sampled during POR, the debug information from the DDR SDRAM interface
is driven on MSRCID[0:4] and MDVAL. This POR value is captured in PORDBGMSR[MEM_SEL] as
described in
source ID appears on MSRCID[0:4] during a RAS or CAS cycle. During any other cycle, the value of
MSRCID[0:4] is all ones, which indicates idle cycles on the address/command interface. Similarly,
MDVAL is asserted during valid data cycles on the DDR interface.
21.4.2.2
If MSRCID1 is low when sampled during POR, debug information from the DDR SDRAM interface is
selected to appear on MECC[0:5] as shown in
(the source ID), appears on MECC[0:4] during a RAS or CAS cycle. During any other cycle the value of
Freescale Semiconductor
(Hex)
Value
0C
0D
00
01
02
03
04
05
06
07
08
09
0A
0B
0E
0F
DDR SDRAM Interface Debug
Section 19.4.1.5, “POR Debug Mode Status Register (PORDBGMSR).”
PCI
PCI Express 2
PCI Express 1
PCI Express 3
Local bus controller
Reserved
Reserved
Security
Configuration space
Reserved
Boot sequencer
Reserved
Reserved
Reserved
Reserved
Local space (DDR)
Debug Information on Debug Pins
Debug Information on ECC Pins
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Source (or Target) Port
Table 21-26. Source and Target ID Values
Figure
(Hex)
Value
1C
1D
14
15
16
17
18
19
1A
1B
1E
1F
10
11
12
13
21-1. In this mode, the ID value of the source port,
Local processor (instruction fetch)
Local processor (data fetch)
Reserved
Reserved
Reserved
DMA
Reserved
System access port (SAP)
eTSEC1
Reserved
eTSEC3
Reserved
Reserved
Reserved
Reserved
Non valid port indicator (reserved for debug info)
Source (or Target) Port
Debug Features and Watchpoint Facility
In this mode, the
21-25