MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 903

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
Note: The eTSEC will not issue an exit pause frame (i.e. pause frame with PTV of 0x0000) once all active
rings have sufficient BDs. Instead, it will wait for the far-end pause timer to expire and start
re-transmission.
15.6.7
Buffer Descriptors
The eTSEC buffer descriptor (BD) is modeled after the MPC8260 Fast Ethernet controller BD for ease of
reuse across the PowerQUICC network processor family. Drawing from the MPC8260 FEC BD
programming model, the eTSEC descriptor base registers point to the beginning of BD rings. The eTSEC
BD also expands upon the MPC8260 BD model to accommodate the eTSEC’s unique features. However,
the 8-byte data BD format is designed to be compatible with the existing MPC8260 BD model.
15.6.7.1
Data Buffer Descriptors
Data buffers are used in the transmission and reception of Ethernet frames (see
Figure
15-134). Data BDs
encapsulate all information necessary for the eTSEC to transmit or receive an Ethernet frame. Within each
data BD there is a status field, a data length field, and a data pointer. The BD completely describes an
Ethernet packet by centralizing status information for the data packet in the status field of the BD and by
containing a data BD pointer to the location of the data buffer. Software is responsible for setting up the
BDs in memory. Because of pre-fetching, a minimum of four buffer descriptors per ring are required. This
applies to both the transmit and the receive descriptor rings. Transmit rings are limited to a maximum size
of 65536 BDs due to BD and frame data prefetching. Software also must have the data pointer pointing to
a legal memory location. Within the status field, there exists an ownership bit which defines the current
state of the buffer (pointed to by the data pointer). Other bits in the status field of the buffer descriptor are
used to communicate status/control information between the eTSEC and the software driver.
Because there is no next BD pointer in the transmit/receive BD (see
Figure
15-135), all BDs must reside
sequentially in memory. The eTSEC increments the current BD location appropriately to the next BD
location to be processed. There is a wrap bit in the last BD that informs the eTSEC to loop back to the
beginning of the BD chain. Software must initialize the TBASE and RBASE registers that point to the
beginning transmit and receive BDs for eTSEC.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
15-173