MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 177

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

4.4.3.14
The PCI clock source inputs, shown in
for the PCIinterface. See Section
that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR
(POR device status register) described in Section 18.4.1.4, “POR Device Status Register (PORDEVSR).”
4.4.3.15
The PCI speed configuration input, shown in
with the PCI clock frequencies in use. The default setting is appropriate for PCI operating above 33 MHz.
For low speed operation (PCI at or below 33 MHZ) this POR configuration input should be low during
HRESET. If this configuration is not set properly, behavior of the PCI interface may be unreliable. Note
that the value latched on this signal during POR is accessible through the memory-mapped PORDEVSR,
described in
Freescale Semiconductor
Functional Signal
PCI_GNT[4]
TSEC3_TXD[0:1]
Functional
Default (1)
Signal
Default (11)
Functional Signal Reset Configuration Name
PCI_GNT[3]
Default (1)
Reset Configuration
Section 19.4.1.4, “POR Device Status Register (PORDEVSR).”
PCI Clock Selection
PCI Speed Configuration
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
cfg_pci_clk
Reset Configuration
cfg_tsec3_prtcl[0:1]
Name
Name
cfg_pci_speed
Table 4-21. eTSEC3 Protocol Configuration
(Binary)
Value
Section 4.4.4.1, “System Clock/PCI
0
1
Table 4-23. PCI Speed Configuration
(Binary)
Value
Table 4-22
Table 4-22. PCI Clock Select
00
01
10
11
Asynchronous mode. PCI_CLK is used as the clock for the PCI interface
Synchronous mode. SYSCLK is used as the clock for the PCI interface. (default)
The eTSEC3 controller operates using 8-bit FIFO protocol.
The eTSEC3 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in
Width”)
The eTSEC3 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in
Width”).
The eTSEC3 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in
Width”) (default).
Table
specify the clock mode (synchronous or asynchronous)
(Binary)
Value
4-23, configures internal logic for proper operation
0
1
PCI frequency at or below 33 MHz
PCI frequency above 33 MHz
(default)
Meaning
Clock” for more information. Note
Meaning
Meaning
Reset, Clocking, and Initialization
Section 4.4.3.11, “eTSEC3
Section 4.4.3.11, “eTSEC3
Section 4.4.3.11, “eTSEC3
4-19