MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 501

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
Length0 J=0
Length1 J=1
Length2 J=0 Extent2 Pointer2
Length3 J=1 Extent3 Pointer3
DESCRIPTOR
Header dword
This figure illustrates various ways that a descriptor may specify data parcels:
The first pointer dword in the descriptor specifies Parcel A using the simplest method—the
parcel is specified directly through Pointer0 and Length0.
The next pointer dword uses a chain of link tables to specify Parcel B. Since J=1, Pointer1 is
used as the address of a link table. The link table specifies several “regular” entries specify-
ing data segments to be concatenated. The last word of the link table is a “next” entry
indicating that the list continues in the next link table. The last entry in the last link table of
the chain has the R bit set.
The last cases illustrate how one pointer in a descriptor can be used to specify multiple par-
cels. Pointer2 and Length2 specify Parcel C, then Parcel D follows immediately afterwards,
with length specified by Extent2. Pointer3 is used for three data parcels (E, F, and G), this
time using link tables.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Extent4
Pointer0
Pointer1
Figure 12-7. Descriptors, Link Tables, and Data Parcels
LINKTABLES
N=1
N=1
R=1
N=1
R=1
SEGMENTS
DATA
Security Engine (SEC) 2.1
PARCELS
Parcel G
Parcel A
Parcel B
Parcel C
Parcel D
Parcel E
Parcel F
Length0
Length1
Length2
Length3
Extent2
Extent3
Extent4
DATA
12-23