MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 1260

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Complete List of Configuration, Control, and Status Registers
B-2
0x0_104C
0x0_1000
0x0_1008
0x0_1010
0x0_1018
0x0_1040
0x0_1044
0x0_1048
0x0_1060
0x08C
0x10C
0x11C
0x000
0x008
0x010
0x018
0x080
0x084
0x088
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
Offset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
EEBACR—ECM CCB address configuration register
ECM CCB data configuration register (EEBDCR)
EEBPCR—ECM CCB port configuration register
ECM CCB debug register (EEBDR)
ECM full threshold count register 0 (EFTCR0)
ECM full threshold count register 1 (EFTCR1)
ECM full threshold count register 2 (EFTCR2)
ECM full threshold count register 3 (EFTCR3)
ECM full threshold count register 4 (EFTCR4)
CS0_BNDS—Chip select 0 memory bounds
CS1_BNDS—Chip select 1 memory bounds
CS2_BNDS—Chip select 2 memory bounds
CS3_BNDS—Chip select 3 memory bounds
CS0_CONFIG—Chip select 0 configuration
CS1_CONFIG—Chip select 1 configuration
CS2_CONFIG—Chip select 2 configuration
CS3_CONFIG—Chip select 3 configuration
TIMING_CFG_3—DDR SDRAM timing configuration 3
TIMING_CFG_0—DDR SDRAM timing configuration 0
TIMING_CFG_1—DDR SDRAM timing configuration 1
TIMING_CFG_2—DDR SDRAM timing configuration 2
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control configuration
2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration
2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval
configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
Table B-1. Memory Map (continued)
Register
Block Base Address: 0x0_2000
e500 Coherency Module
DDR Memory Controller
4-byte
R/W
4-byte
R/W
Mixed
Mixed
Mixed
Mixed
Mixed
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0003
0x0000_0000
0x8000_0010
0x8000_0010
0x8000_0010
0x8000_0010
0x8000_0010
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0011_0105
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0*00_0000
Reset
Freescale Semiconductor
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