WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 3

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WM8900LGEFK/RV

Manufacturer Part Number
WM8900LGEFK/RV
Description
Audio CODECs Ultra Low Power Hi-Fi CODEC
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8900LGEFK/RV

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM8900LGEFK/RV
Manufacturer:
WOLFSON
Quantity:
20 000
Production Data
DESCRIPTION ............................................................................................. 1
FEATURES .................................................................................................. 1
APPLICATIONS ........................................................................................... 1
BLOCK DIAGRAM ....................................................................................... 2
TABLE OF CONTENTS ............................................................................... 3
PIN CONFIGURATION................................................................................. 5
ORDERING INFORMATION ........................................................................ 5
PIN DESCRIPTION ...................................................................................... 6
ABSOLUTE MAXIMUM RATINGS............................................................... 7
RECOMMENDED OPERATING CONDITIONS ........................................... 7
ELECTRICAL CHARACTERISTICS ............................................................ 8
POWER CONSUMPTION .......................................................................... 14
DAC TO HEADPHONE POWER CONSUMPTION .................................... 15
EXTERNAL COMPONENTS...................................................................... 18
RECOMMENDED TEST METHOD FOR TESTING AUDIO OUTPUTS..... 19
AUDIO PATHS OVERVIEW....................................................................... 21
AUDIO INTERFACE TIMING ..................................................................... 23
CONTROL INTERFACE TIMING ............................................................... 25
INTERNAL POWER ON RESET CIRCUIT ................................................ 27
POP-CLICK MINIMISATION CONTROL REGISTERS.............................. 29
DEVICE DESCRIPTION ............................................................................. 30
RESETTING THE CHIP.............................................................................. 87
POWER MANAGEMENT ........................................................................... 87
STOPPING THE MASTER CLOCK ........................................................... 89
REGISTER MAP ........................................................................................ 90
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SYSTEM CLOCK TIMING..................................................................................22
MASTER MODE.................................................................................................23
SLAVE MODE....................................................................................................24
2-WIRE MODE...................................................................................................25
3-WIRE MODE...................................................................................................26
INTRODUCTION................................................................................................30
INPUT SIGNAL PATH........................................................................................30
ANALOGUE TO DIGITAL CONVERTER (ADC).................................................38
DIGITAL MIXING................................................................................................41
DIGITAL TO ANALOGUE CONVERTER (DAC).................................................44
OUTPUT SIGNAL PATH ....................................................................................48
ULTRA-LOW POWER GROUND-REFERENCED HEADPHONE OUTPUT.......56
MASTER BIAS ...................................................................................................57
OPTIMAL PLAYBACK POWER CONSUMPTION ..............................................58
VOLUME UPDATES ..........................................................................................59
HEADPHONE JACK DETECT ...........................................................................61
THERMAL SHUTDOWN ....................................................................................62
GENERAL PURPOSE INPUT/OUTPUT.............................................................63
DIGITAL AUDIO INTERFACE ............................................................................64
AUDIO INTERFACE CONTROL ........................................................................71
CLOCKING AND SAMPLE RATES....................................................................75
FLL.....................................................................................................................81
CONTROL INTERFACE.....................................................................................84
READBACK IN 2-WIRE MODE ..........................................................................86
TABLE OF CONTENTS
PD, August 2008, Rev 4.0
WM8900
3

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