WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 87

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
RESETTING THE CHIP
POWER MANAGEMENT
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The WM8900 can be reset by performing a write of any value to the software reset register
(address 00h). This will cause all register values to be reset to their default values. In addition to
this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default
when the device is powered up.
Table 71 Software Reset Register
The WM8900 has three control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled and bias currents set to the
recommended values. To avoid any pop or click noise, it is important to enable or disable functions
in the correct order (see “Applications Information”). VMID_MODE is the enable for the Vmid
reference, which defaults to disabled and can be enabled as a 2x50kΩ potential divider or, for low
power maintenance of Vref when all other blocks are disabled, as a 2x250kΩ potential divider.
R0 (00h)
Reset
R1 (01h)
Power
Management 1
R2 (02h)
Power
Management 2
REGISTER
ADDRESS
REGISTER
ADDRESS
BIT
8
6
4
3
2
1:0
15
8
15:0
BIT
STARTUP_BIAS_ENA
FLL_ENA
MICB_ENA
BIAS_ENA
VMID_BUF_ENA
VMID_MODE
[1:0]
SYSCLK_ENA
OUT1L_ENA
SW_RESET_
CHIP_ID
LABEL
LABEL
DEFAULT
DEFAULT
0
0
0
0
0
00
0
0
Read: CHIP ID (0x8900)
Write: Software Reset
Bias Startup control.
Normally 0 but can be temporarily set to
one during startup to minimise pops
and clicks.
FLL Digital Enable
0 = Power down
1 = Power up
FLL_OSC_ENA must be enabled
before enabling FLL_ENA. The order is
important.
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
VREF (necessary for all analogue
functions)
0 = Power down
1 = Power up
Provides VMID to input and output
analogue pins when not enabled.
Normally 0 but can be temporarily set to
one during startup to minimise pops
and clicks.
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50kΩ divider (Normal mode)
10 = 2 x 250kΩ divider (Standby mode)
11 = 2 x 5kΩ divider (for fast start-up)
Master Clock Disable
0 = Master clock disabled
1 = Master clock enabled
Left LINEOUT1 Output Buffer
0 = Power down
1 = Power up
PD, August 2008, Rev 4.0
DESCRIPTION
DESCRIPTION
WM8900
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