WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 92
WM8900LGEFK/RV
Manufacturer Part Number
WM8900LGEFK/RV
Description
Audio CODECs Ultra Low Power Hi-Fi CODEC
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8900LGEFKRV.pdf
(117 pages)
Specifications of WM8900LGEFK/RV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
WM8900LGEFK/RV
Manufacturer:
WOLFSON
Quantity:
20 000
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WM8900
w
R0 (00h)
Reset
R1 (01h)
Power Management 1
R2 (02h)
Power Management 2
REGISTER ADDRESS
15:12
15:0
1:0
15
BIT
8
6
4
3
2
8
7
5
4
3
2
1
SW_RESET_CHIP_ID
CHIP_REV [3:0]
STARTUP_BIAS_ENA
FLL_ENA
MICB_ENA
BIAS_ENA
VMID_BUF_ENA
VMID_MODE
[1:0]
SYSCLK_ENA
OUT1L_ENA
OUT1R_ENA
MIXINL_ENA
MIXINR_ENA
INL_ENA
INR_ENA
ADCL_ENA
LABEL
DEFAULT
00
0
0
0
0
0
0
0
0
0
0
0
0
0
Read: CHIP ID (0x8900)
Write: Software Reset
DEVICE_REVISON
4 data bits
Bias Startup control.
Normally 0 but can be temporarily set to
one during startup to minimise pops and
clicks.
FLL Digital Enable
0 = Power down
1 = Power up
FLL_OSC_ENA must be enabled before
enabling FLL_ENA. The order is important.
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
VREF (necessary for all analogue
functions)
0 = Power down
1 = Power up
Provides VMID to input and output
analogue pins when not enabled.
Normally 0 but can be temporarily set to
one during startup to minimise pops and
clicks.
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50kΩ divider (Normal mode)
10 = 2 x 250kΩ divider (Standby mode)
11 = 2 x 5kΩ divider (for fast start-up)
Master Clock Disable
0 = Master clock disabled
1 = Master clock enabled
Left channel LINEOUT1 enable
0 = LINEOUT_1L disabled
1 = LINEOUT_1L enabled
Right channel LINEOUT1 enable
0 = LINEOUT_1R disabled
1 = LINEOUT_1R enabled
Left channel input boost enable
0 = Boost disabled
1 = Boost enabled
Right channel input boost enable
0 = Boost disabled
1 = Boost enabled
Left channel input PGA enable
0 = PGA disabled
1 = PGA enabled (if MIXINL_ENA = 1)
Right channel input PGA enable
0 = PGA disabled
1 = PGA enabled (if MIXINR_ENA = 1)
Enable ADC left channel:
0 = ADC disabled
1 = ADC enabled
DESCRIPTION
PD, August 2008, Rev 4.0
Production Data
92
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