WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 35

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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MICROPHONE BIAS
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones via an external resistor. Refer to the Applications Information section for
recommended external components. The MICBIAS can be enabled or disabled using the
MICB_ENA control bit and the voltage can be selected using the MICB_LVL register bit as detailed
in Table 12.
Table 12 Microphone Bias Control
Note that the maximum source current capability for MICBIAS is 3mA. The external biasing
resistance must be large enough to limit the MICBIAS current to 3mA.
REFERENCE VOLTAGES
All internal analogue input and output circuitry requires a reference voltage AVDD/2 (VMID). This
voltage is generated internally using 5kΩ, 50kΩ or 250kΩ resistors and is buffered as required.
These functions are controlled using register bits VMID_MODE and BIAS_ENA.
Table 13 Reference Voltages
INPUT PGA VOLUME CONTROL
The input PGAs have a gain range from -12dB to +19dB in 1dB steps. The gain on the inverting
and non-inverting inputs to the PGA are always equal and are controlled by the register bits
INL_VOL[4:0] and INR_VOL[4:0]. The left and right input PGAs can be independently muted using
the INL_MUTE and INR_MUTE register bits.
To allow simultaneous volume updates of left and right channels, PGA gains are not altered until a
1 is written to either of the IN_VU bits.
To prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates
will not take place until a zero-crossing is detected. In the event of a long period without zero-
crossings, a timeout function is available. When this function is enabled (using the TOCLK_ENA
register bit), the volume will update after the timeout period if no earlier zero-cross has occurred.
The timeout period is set by TOCLK_RATE. See Table 46 in the “Headphone Jack Detect” section
for the definition of these register bits,
The Input PGA Volume Control register fields are described in Table 14. Note that these
volume/mute settings have no effect on Line inputs routed directly to the boost mixer.
R1 (01h)
Power
Management 1
R21 (15h)
Input Control
R1 (01h)
Power
Management 1
REGISTER
ADDRESS
REGISTER
ADDRESS
3
1:0
BIT
4
8
BIT
BIAS_ENA
VMID_MODE
[1:0]
MICB_ENA
MICB_LVL
LABEL
LABEL
DEFAULT
0
00
0
0
DEFAULT
VREF (necessary for all analogue functions)
0 = V
1 = V
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50kΩ divider (Normal mode)
10 = 2 x 250kΩ divider (Standby mode)
11 = 2 x 5kΩ divider (for fast start-up)
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.65 * AVDD
REF
REF
buffer disabled
buffer enabled
PD, August 2008, Rev 4.0
DESCRIPTION
DESCRIPTION
WM8900
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