WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 71

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
AUDIO INTERFACE CONTROL
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Figure 43 TDM in DSP/PCM Mode B
The register bits controlling audio format, word length and the TDM parameters are summarised in
Table 50.
In Master mode BCLK, ADCLRC and DACLRC are outputs, and the frequency of ADCLRC,
DACLRC and BCLK are set by the fields ADCLRC_RATE, DACLRC_RATE and BCLK_DIV (see
"Clocking and Sample Rates"). In Slave mode BCLK, ADCLRC and DACLRC are inputs.
It is possible to control these clock outputs individually using register bits ADCLRC_DIR,
DACLRC_DIR and BCLK_DIR, allowing mixed master and slave modes for the ADCs and DACs.
See Table 52 for a definition of these fields.
BCLK inverted (AIF_BCLK_INV = 1) is not available in Master Mode (BCLK_DIR = 1).
R4 (04h)
Audio
Interface
1
ADCLRC
ADCDAT
REGISTER
ADDRESS
BCLK
6:5
4:3
13
12
SLOT0 L
BIT
8
7
1 BCLK
AIFADC_TDM
AIFADC_TDM_CHAN
AIF_BCLK_INV
AIF_LRCLK_INV
AIF_WL
[1:0]
AIF_FMT
[1:0]
SLOT0 R
LABEL
SLOT1 L
DEFAULT
10
10
0
0
0
0
1/fs
SLOT1 R
ADC TDM Enable
0 = Normal ADCDAT operation
1 = TDM enabled on ADCDAT
ADCDAT TDM Channel Select
0 = ADCDAT outputs data on slot 0
1 = ADCDAT output data on slot 1
BCLK Invert
0 = BCLK not inverted
1 = BCLK inverted (see note 1)
Right, left and I
polarity
0 = normal LRCLK polarity
1 = invert LRCLK polarity
DSP Mode – mode A/B select
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Digital Audio Interface Format
00 = Right justified
01 = Left justified
10 = I
11 = DSP Mode
2
S Format
PD, August 2008, Rev 4.0
DESCRIPTION
2
S modes – LRCLK
WM8900
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