WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 85

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
The same sequence applies to both Read and Write operations. The only difference is that the
data bits are driven by the controlling device in Write mode, and by the WM8900 in Read mode.
The R/W bit is set to 0 for Write operations and is set to 1 for Read operations. Register Read
operations are only supported from a limited set of registers, as described in Table 68.
Table 68 Readback Registers
2-WIRE SERIAL CONTROL MODE
The WM8900 supports software control via a 2-wire serial bus. 2-wire mode uses the SCLK and
SDIN pins only. Many devices can be controlled by the same bus, and each device has a unique 7-
bit device address (this is not the same as the 7-bit address of each register in the WM8900). To
allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8900
transmits logic 1 by tri-stating the SDIN pin, rather than by pulling it high. An external pull-up
resistor is required to pull the SDIN line high so that the logic 1 can be recognised by the master.
The device address of the WM8900 can be one of two values and is determined by the CSB input
pin when the device is powered up, as described in Table 69. An internal pull-down causes default
selection of the device address. After CSB is sampled on power up, it reverts to a GPIO function
and is not used in 2 wire mode.
Table 69 2-Wire Interface Device Address Selection
The WM8900 operates as a slave device only. The controller indicates the START of data transfer
with a high to low transition on SDIN while SCLK remains high. This indicates that a device
address and data will follow. All devices on the 2-wire bus respond to the START condition and
shift in the next eight bits on SDIN (7-bit address, MSB first + Read/Write bit = 0). Hence the first
byte should equal 0x34 or 0x36. If the device address received matches the address of the
WM8900 (configured by the CSB pin on power up), then the WM8900 responds by pulling SDIN
low on the next clock pulse (ACK). If the address is not recognised, the WM8900 returns to the idle
condition and waits for a new start condition and valid device address.
During a write, once the WM8900 has acknowledged a correct device address, the controller
sends the WM8900 register address (MSB first). The WM8900 then acknowledges the register
address byte by pulling SDIN low for one clock pulse. The controller then sends bits 15-8 of
register data (MSB first), and the WM8900 acknowledges again by pulling SDIN low for one clock
pulse. The controller then sends bits 7-0 of register data (MSB first), and the WM8900
acknowledges again by pulling SDIN low for one clock pulse.
Transfers are complete when there is a low to high transition on SDIN while SCLK is high (STOP).
After a complete sequence the WM8900 returns to the idle state and waits for another start
condition. If a START or STOP condition is detected out of sequence at any point during data
transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
Figure 48 2-Wire Serial Control Interface Writes
R0 (00h)
Reset
R1 (01h)
Power
Management 1
REGISTER
ADDRESS
Low (default)
High
CSB
15:0
15:12
BIT
SW_RESET_
CHIP_ID
CHIP_REV
[3:0]
LABEL
DEVICE ADDRESS
0011010
0011011
DEFAULT
CHIP ID
16 data bits
DEVICE_REVISON
4 data bits
PD, August 2008, Rev 4.0
DESCRIPTION
WM8900
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