WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 78

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
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Table 58 Derivation of Sample Rates in Normal / USB Modes
Note that, in USB mode, the ADC / DAC sample rates do not match exactly with the commonly
used sample rates (eg. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than
0.5%, which is within normal accepted tolerances. Data recorded at 44.100 kHz sample rate and
replayed at 44.118 kHz will experience a slight (sub 0.5%) pitch shift as a result of this difference.
Note USB mode cannot be used to generate a 48kHz samples rate from a 12MHz MCLK. The FLL
should be used in this case.
The user must ensure correct synchronisation of data across the digital interfaces. This is
particularly important when different sample rates are used, as described above.
BCLK CONTROL
In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as
described in Table 59.
BCLK_DIV must be set to an appropriate value to ensure that there are sufficient BCLK cycles to
transfer the complete data words from the ADCs and to the DACs.
Note that, although the ADC and DAC can run at different sample rates, they share the same bit
clock BCLK. In the case where different ADC / DAC sample rates are used, the BCLK frequency
should be set according to the higher of the ADC / DAC bit rates.
12.2880 MHz
11.2896 MHz
12.0000 MHz
2.0480 MHz
SYSCLK
000 = SYSCLK / 1
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
000 = SYSCLK / 1
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
000 = SYSCLK / 1
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
000 = SYSCLK / 1
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
ADC / DAC SAMPLE
RATE DIVIDER
CLOCKING MODE
(256 * Fs)
(256 * Fs)
(272 * Fs)
(256 * Fs)
Normal
Normal
Normal
USB
PD, August 2008, Rev 4.0
48 kHz
32 kHz
24 kHz
16 kHz
12 kHz
Not used
8 kHz
Reserved
44.1 kHz
Not used
22.05 kHz
Not used
11.025 kHz
8.018 kHz
Not used
Reserved
44.118 kHz
Not used
22.059 kHz
Not used
11.029 kHz
8.021 kHz
Not used
Reserved
8 kHz
Not used
Not used
Not used
Not used
Not used
Not used
Reserved
SAMPLE RATE
Production Data
ADC / DAC
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