WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet
WJLXT384LE.B1-868635
Specifications of WJLXT384LE.B1-868635
Available stocks
Related parts for WJLXT384LE.B1-868635
WJLXT384LE.B1-868635 Summary of contents
Page 1
Cortina Systems Short-Haul PCM Transceiver with Jitter Attenuation (JA) Datasheet Product Features Octal T1/E1/J1 Pulse-Code Modulation (PCM) Transceiver with Jitter Attenuation for use in both 1.544 MBps (T1) and 2.048 MBps (E1) applications 16 fully-independent receiver/transmitters Support for E1 standards: ...
Page 2
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Applications SONET/SDH tributary interfaces Digital cross connects Public/private switching trunk line interfaces ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA Microwave transmission systems M13, ...
Page 3
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
Page 4
... Microprocessor-Standard Bus and Interface Signals ......................................................... 22 5.3 Framer/Mapper Signals ...................................................................................................... 25 5.3.1 Bipolar vs. Unipolar Operation - Receive Side ...................................................... 25 5.3.2 Bipolar vs. Unipolar Operation - Transmit Side ..................................................... 26 5.3.3 Framer/Mapper Signals - Details ........................................................................... 27 5.4 Line Interface Unit Signals.................................................................................................. 32 5.5 Clocks and Clock-Related Signals...................................................................................... 35 5.6 Configuration and Mode-Select Signals ............................................................................. 37 5.7 Signal Loss and Line-Code-Violation Signals..................................................................... 39 5 ...
Page 5
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 6.4.4.2 Transmitter Output Low-Power Options................................................. 53 6.5 Line-Interface Protection..................................................................................................... 53 6.6 Jitter Attenuation................................................................................................................. 56 6.7 Loopbacks .......................................................................................................................... 58 6.7.1 Analog Loopback ................................................................................................... 58 6.7.2 Digital Loopback .................................................................................................... 59 6.7.3 Remote Loopback.................................................................................................. ...
Page 6
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 13.0 Mask Specifications .................................................................................................................. 114 14.0 Jitter Performance..................................................................................................................... 117 15.0 Recommendations and Specifications.................................................................................... 121 16.0 Mechanical Specifications........................................................................................................ 122 17.0 Abbreviations and Acronyms................................................................................................... 124 ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM ...
Page 7
... Receiver Bipolar/Unipolar I/O Signal Functions ............................................................................ 20 5 Transmitter Bipolar/Unipolar I/O Signal Functions ........................................................................ 21 6 Microprocessor-Standard Bus and Interface Signals .................................................................... 23 7 Framer/Mapper Receive Signals ................................................................................................... 27 8 Framer/Mapper Transmit Signals .................................................................................................. 30 9 Line Interface Unit Signals............................................................................................................. 33 10 Clocks and Clock-Related Signals ................................................................................................ 36 11 Configuration and Mode-Select Signals ........................................................................................ 38 12 Signal Loss and Line-Code-Violation Signals ...
Page 8
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 52 Device Identification Register (IDR) .............................................................................................. 87 53 Instruction Register (IR)................................................................................................................. 88 54 JTAG Timing Characteristics......................................................................................................... 88 55 Absolute Maximum Ratings........................................................................................................... 89 56 Recommended Operating Condition ............................................................................................. 89 57 LXT384 Transceiver ...
Page 9
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 1 LXT384 Transceiver High-Level Block Diagram............................................................................ 13 2 LXT384 Transceiver Detailed Block Diagram................................................................................ 14 3 LXT384 Transceiver 144-Pin Assignments ................................................................................... 16 4 LXT384 Transceiver Plastic Ball Grid Array (PBGA) Pin Assignments ...
Page 10
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Revision History First release of this document from Cortina Systems, Inc. • Revised package information on Page 1. • Changed text in Chapter 1.0, “Audience and Purpose” on Page 11. • ...
Page 11
... LXD384 - Evaluation Board for Octal T1/E1 Applications - Developer Manual ® Cortina Systems LXT380/1/4/6/8 Redundancy Applications - Application Note ® Cortina Systems LXT380/4 Octal T1/E1 LIUs - Interfacing with the Transwitch Octal Framers - Application Note ® Cortina Systems LXT384 Octal LIU and Cortina Systems Slow Power-Up Rise Time - Application Note ® ...
Page 12
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 2.0 Product Summary The LXT384 Transceiver is designed for use in 1.544 MBps (T1) or 2.048-Mbps (E1) applications. It incorporates eight independent receivers and eight independent transmitters in either a single ...
Page 13
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure high-level block diagram of the LXT384 Transceiver. Figure 1 LXT384 Transceiver High-Level Block Diagram ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA) ...
Page 14
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure detailed block diagram of the LXT384 Transceiver. Figure 2 LXT384 Transceiver Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP7 RRING7 TTIP7 TRING7 RTIP6/RRING6 TTIP6/TRING6 RTIP5/RRING5 TTIP5/TRING5 RTIP4/RRING4 ...
Page 15
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 3.0 Pin Assignments and Package The LXT384 Transceiver has two packages: • A 144-pin Low-Profile Octal-Flat Package, or ‘LQFP’ • A 160-ball Plastic Ball Grid Array package, or ‘PBGA’ For signal ...
Page 16
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 3 shows a top view of the LXT384 Transceiver Low-profile Octal Flat Pack (LQFP) package, with pin assignments. Figure 3 LXT384 Transceiver 144-Pin Assignments Figure 4 shows a bottom view ...
Page 17
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 4 LXT384 Transceiver Plastic Ball Grid Array (PBGA) Pin Assignments RCLK RPOS RNEG TVCC TCLK TPOS TNEG TVCC ...
Page 18
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 4.0 Multi-Function Pins The LXT384 Transceiver has several pins that have more than one name and more than one function, depending on the mode selected. This chapter lists the multi-function pins. ...
Page 19
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 3 Operating Mode-Specific Signal Names HDB3 / 88 H12 CODEN AMI select JA path 87 J11 JASEL select 28 K1 LOOP7 27 J1 LOOP6 26 J2 LOOP5 Loopback 25 J3 ...
Page 20
... RDATA7 RDATA6 RDATA5 RDATA4 Receive positive data output RDATA3 RDATA2 RDATA1 RDATA0 RCLK7 RCLK6 RCLK5 RCLK4 Receive clock output RCLK3 RCLK2 RCLK1 RCLK0 4.2 Framer/Mapper I/O Pins Section 5.3.1, Bipolar vs. Detect bipolar violations output Receive data output Receive clock output Page 20 ...
Page 21
... UBS2 unipolar I/O mode is selected. UBS1 UBS0 TDATA7 TDATA6 TDATA5 TDATA4 Transmit positive data input TDATA3 TDATA2 TDATA1 TDATA0 TCLK7 TCLK6 TCLK5 TCLK4 Transmit clock input TCLK3 TCLK2 TCLK1 TCLK0 4.2 Framer/Mapper I/O Pins Transmit data input Transmit clock input Page 21 ...
Page 22
... Signal Groupings Signal groupings discussed in this chapter include the following: Section 5.2, Microprocessor-Standard Bus and Interface Signals Section 5.3, Framer/Mapper Signals Section 5.4, Line Interface Unit Signals Section 5.5, Clocks and Clock-Related Signals Section 5.6, Configuration and Mode-Select Signals Section 5.7, Signal Loss and Line-Code-Violation Signals Section 5 ...
Page 23
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 6 Microprocessor-Standard Bus and Interface Signals (Sheet Signal QFP Name Pin RDY / ACK 83 SDO ...
Page 24
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 6 Microprocessor-Standard Bus and Interface Signals (Sheet LOOP7 LOOP6 LOOP5 LOOP4 LOOP3 24 D3 ...
Page 25
... LEN0 1. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. OD: Open Drain 5.3 Framer/Mapper Signals Framer/mapper signals are used to interface the LXT384 Transceiver to a framer/mapper. 5.3.1 Bipolar vs. Unipolar Operation - Receive Side lists receive-side framer/mapper signals, which can connect to a framer/mapper using either bipolar or unipolar interface connections ...
Page 26
... RDATA does not distinguish between a positive or a negative pulse on the line. In this case, the signal flow occurs as follows: 1. RDATA and RCLK connect the LXT384 Transceiver to a framer/mapper, while BPV acts as a bipolar violation detector. The LXT384 Transceiver internally decodes HDB3/AMI. ...
Page 27
... Revision 6.0 30 January 2008 5.3.3 Framer/Mapper Signals - Details • Table 7 lists and describes the LXT384 Transceiver framer/mapper receive signals. • Table 8 lists and describes the LXT384 Transceiver framer/mapper transmit signals. For multi-function pins, the pin name in Table 7 Framer/Mapper Receive Signals (Sheet ...
Page 28
... LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 7 Framer/Mapper Receive Signals (Sheet Signal QFP Name BPV7 / 141 RNEG7 BPV6 / RNEG6 BPV5 / 105 RNEG5 BPV4 / RNEG4 BPV3 / RNEG3 BPV2 / RNEG2 BPV1 / RNEG1 BPV0 / RNEG0 RDATA7 / RPOS7 RDATA6 / RPOS6 RDATA5 / RPOS5 RDATA4 / ...
Page 29
... LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA) 5.3 Framer/Mapper Signals TM TM Page 29 ...
Page 30
... LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 8 Framer/Mapper Transmit Signals (Sheet Signal QFP Name TCLK7 TCLK6 TCLK5 100 TCLK4 107 TCLK3 TCLK2 TCLK1 TCLK0 ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA) PBGA Signal Pin ...
Page 31
... LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 8 Framer/Mapper Transmit Signals (Sheet Signal QFP Name / UBS7 144 TNEG7 / UBS6 TNEG6 / UBS5 102 TNEG5 / UBS4 109 TNEG4 / UBS3 TNEG3 / UBS2 TNEG2 / UBS1 TNEG1 / UBS0 TNEG0 ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA) ...
Page 32
... LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 8 Framer/Mapper Transmit Signals (Sheet Signal QFP Name TNEG7 / 144 UBS7 TNEG6 / UBS6 TNEG5 / 102 UBS5 TNEG4 / 109 UBS4 TNEG3 / UBS3 TNEG2 / UBS2 TNEG1 / UBS1 TNEG0 / UBS0 / TPOS7 TDATA7 / TPOS6 TDATA6 / TPOS5 TDATA5 ...
Page 33
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 9 Line Interface Unit Signals (Sheet Signal QFP Name Pin LOOP7 LOOP6 LOOP5 LOOP4 D3 ...
Page 34
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 9 Line Interface Unit Signals (Sheet Signal QFP Name Pin RRING7 138 RRING6 133 RRING5 126 RRING4 121 RRING3 66 RRING2 61 RRING1 54 RRING0 49 RTIP7 ...
Page 35
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 5.5 Clocks and Clock-Related Signals Table 10 lists and describes LXT384 Transceiver clocks and clock-related signals. Note: Within this table, ‘RCLK’ references RCLK7:0 and ‘TCLK’ references TCLK7:0. Each RCLK and TCLK ...
Page 36
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 10 Clocks and Clock-Related Signals (Sheet Signal QFP PBGA Name Pin Ball CLKE 115 E13 ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation ...
Page 37
... For information on RCLK, see 5.3, Framer/Mapper Shift Clock Input. For information on SCLK, see 5.2, Microprocessor-Standard Bus and Interface Signals. Transmit Clock Input 7:0. For information on TCLK, see 5.3, Framer/Mapper print indicates the signal being discussed. blue bold Signals 6.5, Line-Interface Protection. Signals. Signals. Page 37 ...
Page 38
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 11 Configuration and Mode-Select Signals (Sheet Signal QFP Name Pin / INTL / CODEN 88 MOT CODEN / / INTL 88 MOT / JASEL ...
Page 39
... For timing diagrams, see Section 11.2, Host Processor Mode - Parallel Interface Timing D12 Unipolar/Bipolar Select Input 7:0. B12 DI For information on the UBS signals, see N12 Mapper Signals. L12 L3 N3 5.7 Signal Loss and Line-Code- Violation Signals Operating Mode and Ground. CC Section 5.3, Framer/ Page 39 ...
Page 40
... Section 6.3.3, Receiver Loss-Of-Signal Receive Clock Output 7:0. For information on how RCLK is used for clock and data recovery, see Section 5.3, Framer/Mapper 5.7 Signal Loss and Line-Code- Violation Signals Table 13. A4 must be connected Section 5.2, Signals). Section 5.3, Framer/ Signals. Detector.) Signals. Page 40 ...
Page 41
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 13 Performance-Monitoring Selections with A3:0 Pins Signal QFP PBGA Name Pin Ball 5.8 Power and Grounds Table 14 ...
Page 42
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 For low-noise operation, the LXT384 Transceiver is designed so that each transmitter has its own power and its own ground. These pins are not necessarily internally connected. For example, for channel ...
Page 43
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 15 JTAG Analog Interface Test Signals Signal QFP PBGA Name Pin AT2 93 AT1 94 1. AI: Analog Input. AO: Analog Output. Table 16 JTAG Digital Interface Test Signals Signal ...
Page 44
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 18 LXT384 Transceiver Line Length Equalizer Inputs LEN2 LEN1 LEN0 Line ...
Page 45
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 6.0 Functional Description This functional description chapter follows the flow of signals through an LXT384 Transceiver. This chapter discusses the following topics: • Section 6.1, Functional Overview • Section 6.2, Initialization ...
Page 46
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 6.2 Initialization and Reset Initialization for the LXT384 Transceiver occurs as follows: 1. During power-up, the LXT384 Transceiver unknown state until the power supply reaches approximately 60% of ...
Page 47
... ITU G.823, as shown in Test Specifications, — Depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the HDB3/AMI decoder, and may be output to the framer as either bipolar or unipolar data. 6.3.3 Receiver Loss-Of-Signal Detector The LXT384 Transceiver loss-of-signal (LOS) detector circuit is designed to detect loss of signals in both analog and digital domains. This circuit is independent of the data slicer. • ...
Page 48
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 returns to Low when the incoming signal has transitions when the signal level is equal or greater than 250 mV for more than 32 consecutive pulse intervals. This mode is activated ...
Page 49
... Transmitter The LXT384 Transceiver has eight identical transmitters. ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA Table 42. Table 46. Section 6.3.3, Receiver Loss-Of-Signal Section 5.3, Framer/Mapper Signals.) 6.4 Transmitter Table 47.) Detector) detects an Page 49 ...
Page 50
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 6.4.1 Transmitter Clocking The eight low-power transmitters of the LXT384 Transceiver are identical. Transmit data is clocked serially into the device at TPOS/TNEG in bipolar mode TDATA in unipolar ...
Page 51
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 5 50% AMI Encoding Each output driver is supplied by its own TVCC and TGND power-supply pins. The transmit pulse shaper is bypassed if no MCLK is supplied. When in ...
Page 52
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 • Apply a clock to one of these signals: TPOS, TNEG, TCLK, or MCLK. • Set one of these signals low: TPOS, TNEG, TCLK, or OE. 6.4.2.1 LXT384 Transceiver Hardware Mode ...
Page 53
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 6.4.2.4 Power Sequencing For the LXT384 Transceiver, sequence TVCC first, then VCC second or at the same time as TVCC, to prevent excessive current draw. 6.4.3 Transmitter Outputs A transmitter transmits ...
Page 54
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 For some power-up operations, on rare occasions there is no activity for several seconds on all of the following transmit-side pins: TPOS, TNEG, TCLK, and MCLK. If this lack of activity ...
Page 55
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 6 LXT384 Transceiver External Transmit/Receive Line Circuitry TVCC 68μF 1 0.1μF 3.3V VCC 0.1μF GND Transceiver (ONE CHANNEL) 1 Common decoupling capacitor for all TVCC and TGND pins. 2 Typical ...
Page 56
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 20 lists the component values to use with the of power used and the type of cable with which the component is used. Table 20 Component Values to Use with ...
Page 57
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 7 Jitter Attenuator TPOSi RPOSi TNEGi RNEGi TCLKi RCLKi JASEL0 MCLK When the LXT384 Transceiver is in the: • Host Processor mode: — The Global Control Register (GCR, ...
Page 58
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 — ITU-T G.736 — ITU-T G.742, when used with the SXT6234 E2-E1 mux/demux. — ITU-T G.783, combined jitter when used with the SXT6251 21E1 mapper. • BAPT220 The LXT 384 Transceiver ...
Page 59
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 8 LXT384 Transceiver Analog Loopback TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 6.7.2 Digital Loopback The digital loopback function is available in the Host Processor mode only. As ...
Page 60
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 6.7.3 Remote Loopback As Figure 10 shows, when a remote loopback is selected, the RCLK, RPOS, and RNEG outputs route to the transmit circuits, and data are output on the TTIP ...
Page 61
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 processor, TAOS does not work because wait states cannot be added. To ensure the output frequency is within specification limits, MCLK must have the applicable stability. 2. When TAOS is active, ...
Page 62
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 6.8.3 TAOS Generation with Digital Loopback Figure 13 shows how the TAOS mode affects the receive path after digital loopback. TAOS with Digital Loopback for Figure 13 MCLK TCLK TPOS TNEG ...
Page 63
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Performance Monitoring through Remote Loopback. Performance monitoring of either (1) analog line inputs RTIP/RRING to any one of channels 1 through 7 or (2) analog line outputs TTIP/TRING from any one ...
Page 64
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 7.0 Operating Mode Summary This section discusses the following operating modes: • Section 7.1, Interfacing with 5 V Logic • Section 7.2, Hardware Mode • Section 7.3, Hardware Mode Settings • ...
Page 65
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 22 LXT384 Transceiver Operation Mode Summary (Sheet MCLK TCLK H Clocked H Clocked Hardware mode only. ...
Page 66
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 — Write cycle, ACK indicates the LXT384 Transceiver has accepted the write data from the Motorola* processor. • Intel* processor and RDY is: — Low, the LXT384 Transceiver indicates to the ...
Page 67
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 14 Host Processor Mode - Serial Interface Read Timing 7.5 Interrupt Handling 7.5.1 Interrupt Sources Interrupt sources include the following: 1. Status change in the LOS (Loss of Signal) Status ...
Page 68
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 (if one is not already pending). When an interrupt occurs, the INT pin is asserted low. The output circuitry of the INT pin consists of an active pull-down device (an open ...
Page 69
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 8.0 Registers This chapter discusses the LXT384 Transceiver registers. 8.1 Register Summary Table 24 lists LXT384 Transceiver registers by the hex address of each. Table 24 LXT384 Transceiver Register Summary Address ...
Page 70
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 25 groups the LXT384 Transceiver registers by function and lists the bit names. Table 25 Register Bit Names Register Mne- Name RW monic ID, Reset, and Control Registers ID ID ...
Page 71
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 8.2 Register Addresses Table 26 lists the register names and register addresses on: • Pins A7:1 (used for the LXT384 Transceiver Host Processor mode with a serial interface) • Pins A7:0 ...
Page 72
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 8.3 Register Descriptions Table 27 ID Register 00h Bit Name Identification. The identification register contains a unique revision code that is factory programmed for each revision of the LXT384 ...
Page 73
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 32 DFM Status Monitor Register, DFM (05h) for LXT384 Transceiver Bit Name Respective bit(s) are set to “1” every time the short circuit monitor detects a valid DFM7- 7-0 secondary ...
Page 74
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 37 Reset Register, RES - 0Ah Bit Name Reset. The RES7:0 bits are used to set all LXT384 Transceiver registers to their default values. 7:0 RES7:0 For details on non-multiplexed ...
Page 75
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 38 lists and describes the A3:0 bits that can be used to monitor the performance of one of either Receivers 1 through 7 or one of Transmitters 1 through 7, ...
Page 76
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 39 Digital Loopback Register 0Ch Bit Name Digital Loopback. 7:0 DL7:0 During digital loopback, LOS and TAOS stay active and independent of TCLK, while data received on TPOS, ...
Page 77
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 42 Global Control Register, GCR - 0Fh Bit Name 7 - Reserved. Receive Alarm Indication Signal Enable. This bit controls automatic AIS insertion in the receive path when LOS occurs. ...
Page 78
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 43 Pulse Shaping Indirect Address Register, PSIAD (10h) 1 Bit Name 0-2 LENAD 0 power-on reset the register is set to “0”. Table 44 ...
Page 79
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 46 AIS Status Monitor Register, AIS - 13h Bit Name Alarm Indication Signal Status Monitor. 7:0 AIS7:0 Table 47 AIS Interrupt Enable Register, AISIE - 14h Bit Name Alarm Indication ...
Page 80
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 9.0 JTAG Boundary Scan 9.1 Overview The LXT384 Transceiver supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition ...
Page 81
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 49 TAP State Description State In this state the test logic is disabled. The device is set to normal operation mode. While in Test Logic Reset this state, the instruction ...
Page 82
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 16 JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE 9.4 JTAG Register Description The following paragraphs describe each of the registers represented in ® Cortina Systems LXT384 ...
Page 83
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 9.4.1 9.4.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns ...
Page 84
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 50 Boundary Scan Register (BSR) (Sheet Pin Bit # Signal 25 TCLK0 26 TPOS0 27 TNEG0 28 RCLK0 29 RPOS0 30 N/A 31 RNEG0 32 LOS0 33 ...
Page 85
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 50 Boundary Scan Register (BSR) (Sheet Pin Bit # Signal 58 TCLK5 59 TPOS5 60 TNEG5 61 RCLK5 62 RPOS5 63 N/A 64 RNEG5 65 LOS5 66 ...
Page 86
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 50 Boundary Scan Register (BSR) (Sheet Pin Bit # Signal 91 TCLK6 92 MCLK 93 MODE Figure ...
Page 87
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 51 shows the 16 possible control codes and the corresponding operation on the analog port. Table 51 Analog Port Scan Register (ASR) ASR Control Code 11111 11110 11101 11100 11011 ...
Page 88
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 53 Instruction Register (IR) Instruction EXTEST INTEST_ANALOG SAMPLE / PRELOAD IDCODE BYPASS Table 54 JTAG Timing Characteristics Parameter Cycle time J-TMS/J-TDI to J-TCK rising edge time J-CLK rising to J-TMS/L-TDI ...
Page 89
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 10.0 Electrical Characteristics The tables in this chapter specify the electrical characteristics of the LXT384 Transceiver. The specifications are guaranteed by test except, where noted, by design. The minimum and maximum ...
Page 90
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 56 Recommended Operating Condition (Sheet Parameter DC supply core voltage for VCC1:0 and VCCIO1:0 (referenced to ground) DC supply voltage rise time DC supply voltage for TVCC7:0 ...
Page 91
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 3 Table 58 Load Power Consumption Parameter 1:2 Transformer Load TVCC Typical 760 75 Ω 1270 3.3V 640 120 Ω 1110 1000 75 Ω 1730 5.0 V (1:2 transformer) 820 120 ...
Page 92
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 59 DC Characteristics Parameter Special Input Conditions for JASEL, LOOP7:0, and MODE High-level input voltage Low-level input current High-level input current 1. Output drivers output CMOS logic levels into CMOS ...
Page 93
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 61 LXT384 Transceiver T1 Transmit Transmission Characteristics (Sheet Parameter Ratio of positive to negative pulse amplitude Difference between pulse sequences Pulse width variation at half amplitude 10Hz ...
Page 94
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 62 LXT384 Transceiver E1 Receive Transmission Characteristics (Sheet Parameter Low limit input jitter 2.4 kHz 1 tolerance 18 kHz ...
Page 95
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 63 LXT384 Transceiver T1 Receive Transmission Characteristics (Sheet Parameter LOS delay time LOS reset Receive intrinsic jitter, RCLK output Bipolar mode Receive path delay Unipolar mode 1. ...
Page 96
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 11.0 Timing Characteristics This chapter discusses the following timing characteristics: • Section 11.1, LXT384 Transceiver Timing • Section 11.2, Host Processor Mode - Parallel Interface Timing — Section 11.2.1, Intel* Processor ...
Page 97
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 19 LXT384 Transceiver - Transmit Timing TCLK TPOS TNEG Table 65 lists receive timing characteristics for the LXT384 Transceiver. Table 65 LXT384 Transceiver Receive Timing Characteristics Parameter Clock recovery capture ...
Page 98
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 20 LXT384 Transceiver - Receive Timing RCLK tPWH tSUR RPOS RNEG CLKE = 1 RPOS RNEG CLKE = 0 11.2 Host Processor Mode - Parallel Interface Timing This sections gives ...
Page 99
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Processor - Read Timing Characteristics Table 66 Intel* Parameter Address setup time to latch Valid address latch pulse width Latch active to active read setup time Chip select setup time to ...
Page 100
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 21 Intel* Processor Non-Multiplexed Interface - Read Timing ALE (Connected High INT tDRDY Tristate RDY ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul ...
Page 101
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for the Intel* processor in the Host Processor mode, with a multiplexed interface, and a read cycle takes place. Processor Multiplexed Interface - Read Timing ...
Page 102
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 67 lists write timing characteristics for the Intel* processor. Processor - Write Timing Characteristics Table 67 Intel* Parameter Address setup time to latch Valid address latch pulse width Latch active ...
Page 103
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for the Intel* processor in the Host Processor mode, with a non- multiplexed interface, and a write cycle takes place. Processor Non-Multiplexed Interface - Write ...
Page 104
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for the Intel* processor in the Host Processor mode, with a multiplexed interface, and a write cycle takes place. Processor Multiplexed Interface - Write Timing ...
Page 105
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 11.2.2 Motorola* Processor - Parallel Interface Timing Table 68 lists read timing characteristics for the Motorola* processor. Table 68 Motorola* Processor - Read Timing Characteristics Parameter Address setup time to address ...
Page 106
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for the Motorola* processor in the Host Processor mode, with a non-multiplexed interface, and a read cycle takes place. Figure 25 Motorola* Processor Non-Multiplexed Interface ...
Page 107
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for the Motorola* processor in the Host Processor mode with a multiplexed interface, and a read cycle takes place. Figure 26 Motorola Processor Multiplexed Interface ...
Page 108
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 69 lists write timing characteristics for the Motorola* processor. Table 69 Motorola Processor - Write Timing Characteristics Parameter Address setup time to address strobe Address hold time to address strobe ...
Page 109
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for the Motorola* processor in the Host Processor mode, with a non-multiplexed interface, and a write cycle takes place. Figure 27 Motorola* Processor Non-Multiplexed Interface ...
Page 110
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for the Motorola* processor in the Host Processor mode, with a multiplexed interface, and a write cycle takes place. Figure 28 Motorola* Processor Multiplexed Interface ...
Page 111
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 11.3 Host Processor Mode - Serial Interface Timing Table 70 lists serial I/O timing for a Motorola* or Intel* processor in the Host Processor mode with a serial interface. Table 70 ...
Page 112
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure timing diagram for serial output from the Host Processor interface. Figure 30 Serial Output Timing CLKE = SCLK CS SDO CLKE = ...
Page 113
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 12.0 Line-Interface-Unit Circuit Specifications Table 71 lists specifications for the LIU circuits with which the LXT384 Transceiver is designed to operate. (For a diagram of an LIU circuit to be used ...
Page 114
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 13.0 Mask Specifications This chapter discusses the specifications for the mask into which the LXT384 Transceiver transmitter output pulses must fit. The mask specification has two parts. • Part 1 (Table ...
Page 115
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 31 E1, ITU G.703 Mask Template V = 100% 50% 0% Table 74 T1.102 1.544 Mbit/s Pulse Mask Specifications for LXT384 Transceiver Test load impedance Nominal peak mark voltage Nominal ...
Page 116
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 32 T1, T1.102 Mask Templates for LXT384 -0.80 -0.60 -0.40 ® Cortina Systems LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA) 1.20 1.00 0.80 0.60 0.40 0.20 0.00 ...
Page 117
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 14.0 Jitter Performance This chapter includes tables and figures on jitter performance. For more information on jitter, see: • Section 6.6, Jitter Attenuation • Table 42 in Section 8.0, Registers Table ...
Page 118
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Table 75 LXT384 Transceiver Jitter Attenuator Characteristics (Sheet Parameter T1 jitter attenuation Output Jitter in remote loopback 1. Guaranteed by design and other correlation methods. Table 76 LXT384 ...
Page 119
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 34 shows the typical jitter transfer performance for the LXT384 Transceiver. Figure 34 LXT384 Transceiver Jitter Transfer Performance Figure 35 shows the typical jitter performance of the LXT384 Transceiver when ...
Page 120
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 As Figure 35 shows, the LXT384 Transceiver output jitter is below the specified jitter requirement (indicated in the figure by the dark line). Figure 35 LXT384 Transceiver Output Jitter for ETSI ...
Page 121
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 15.0 Recommendations and Specifications • AT&T* - Technical Reference 62411 “Private Line Services - Description and Interface Specification”, December 1990. • ANSI T1.102 - 199X Digital Hierarchy Electrical Interface • ANSI ...
Page 122
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 16.0 Mechanical Specifications Figure 36 Dimensions for 144-Pin Low Octal Flat Package (LQFP) 144-Pin LQFP • Part Number LXT384LE • Extended Temperature Range (-40 D/2 E1/2 E1 ...
Page 123
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 Figure 37 Dimensions for 160-Ball Plastic Ball Grid Array (BGA) 160-Pin PBGA • Part Number LXT384BE o • Extended Temperature Range (- 15.00 13.00 ±0.20 4.72 ±0.10 PIN ...
Page 124
LXT384 Transceiver Datasheet 248994, Revision 6.0 30 January 2008 17.0 Abbreviations and Acronyms Table 77 lists abbreviations and acronyms and their meanings. Table 77 Abbreviations, Acronyms, and Meanings Abbreviation or Acronym AIS AMI B8ZS BPV ESD FCS FIFO HDB3 I/O ...
Page 125
For additional product and ordering information: www.cortina-systems.com ~ End of Document ~ TM ...