WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 83

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
9.4.1
Table 50
Cortina Systems
9.4.1 Boundary Scan Register (BSR)
The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to
apply and read test patterns to/from the board. Each pin is associated with a scan cell in the
BSR register. Bidirectional pins or tristate pins require more than one position in the register.
Table 50
first.
The Analog Test Port can be used to verify continuity across the coupling transformer’s
primary winding as shown in
voltage will appear at AT2 for a given load. This, in effect, tests the continuity of a receive or
transmit interface.
Boundary Scan Register (BSR) (Sheet 1 of 4)
®
Bit #
10
12
13
14
15
16
17
18
19
20
21
22
23
24
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
11
0
1
2
3
4
5
6
7
8
9
RNEG1
LOOP0
LOOP0
LOOP1
LOOP1
LOOP2
LOOP2
LOOP3
LOOP3
LOOP4
LOOP4
LOOP5
LOOP5
LOOP6
LOOP6
LOOP7
LOOP7
TPOS1
TNEG1
RPOS1
TCLK1
RCLK1
Signal
shows the BSR scan cells and their functions. Data into the BSR is shifted in LSB
LOS1
N/A
N/A
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
-
I
I
I
-
PDOENB
Figure
Symbol
RPOS1
RNEG1
PADD0
PADD1
PADD2
PADD3
PADD4
PADD5
PADD6
PADD7
TPOS1
TNEG1
RCLK1
TCLK1
PDO0
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
LOS1
HIZ1
Bit
17. By applying a stimulus to the AT1 input, a known
PDOENB controls the LOOP0 through LOOP7 pins.
Setting PDOENB to “0” configures the pins as outputs. The
output value to the pin is set in PDO[0...7].
Setting PDOENB to “1” tristates all the pins. The input value to
the pins can be read in PADD[0...7].
HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting
HIZ1 to “0” enables output on the pins. Setting HIZ1 to “1”
tristates the pins.
TM
TM
Comments
9.4 JTAG Register Description
Page 83