WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 5

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
7.0
8.0
9.0
10.0 Electrical Characteristics............................................................................................................ 89
11.0 Timing Characteristics................................................................................................................ 96
12.0 Line-Interface-Unit Circuit Specifications ............................................................................... 113
Cortina Systems
6.5
6.6
6.7
6.8
6.9
6.10
Operating Mode Summary.......................................................................................................... 64
7.1
7.2
7.3
7.4
7.5
Registers ...................................................................................................................................... 69
8.1
8.2
8.3
JTAG Boundary Scan.................................................................................................................. 80
9.1
9.2
9.3
9.4
11.1
11.2
11.3
Line-Interface Protection..................................................................................................... 53
Jitter Attenuation................................................................................................................. 56
Loopbacks .......................................................................................................................... 58
6.7.1
6.7.2
6.7.3
Transmit All Ones Operations............................................................................................. 60
6.8.1
6.8.2
6.8.3
Performance Monitoring ..................................................................................................... 62
Hitless Protection Switching ............................................................................................... 63
Interfacing with 5 V Logic.................................................................................................... 64
Hardware Mode .................................................................................................................. 64
Hardware Mode Settings .................................................................................................... 64
Host Processor Modes ....................................................................................................... 65
7.4.1
7.4.2
Interrupt Handling ............................................................................................................... 67
7.5.1
7.5.2
7.5.3
Register Summary .............................................................................................................. 69
Register Addresses ............................................................................................................ 71
Register Descriptions.......................................................................................................... 72
Overview............................................................................................................................. 80
Architecture......................................................................................................................... 80
TAP Controller .................................................................................................................... 80
JTAG Register Description ................................................................................................. 82
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
LXT384 Transceiver Timing................................................................................................ 96
Host Processor Mode - Parallel Interface Timing ............................................................... 98
11.2.1 Intel* Processor - Parallel Interface Timing ........................................................... 98
11.2.2 Motorola* Processor - Parallel Interface Timing .................................................. 105
Host Processor Mode - Serial Interface Timing ................................................................ 111
®
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
6.4.4.2
Analog Loopback ................................................................................................... 58
Digital Loopback .................................................................................................... 59
Remote Loopback.................................................................................................. 60
TAOS Generation .................................................................................................. 60
TAOS Generation with Analog Loopback .............................................................. 61
TAOS Generation with Digital Loopback ............................................................... 62
Host Processor Mode - Parallel Interface .............................................................. 65
7.4.1.1
Host Processor Mode - Serial Interface................................................................. 66
Interrupt Sources ................................................................................................... 67
Interrupt Enable ..................................................................................................... 67
Interrupt Clear........................................................................................................ 68
Boundary Scan Register (BSR) ............................................................................. 83
Analog Port Scan Register (ASR).......................................................................... 86
Device Identification Register (IDR)....................................................................... 87
Bypass Register (BYR).......................................................................................... 87
Instruction Register (IR)......................................................................................... 87
Transmitter Output Low-Power Options................................................. 53
Host Processor Mode - Parallel Interface, Intel* Processor................... 66
TM
TM
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