WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 28

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Table 7
Cortina Systems
Framer/Mapper Receive Signals (Sheet 2 of 2)
®
1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output.
RDATA7 /
RDATA6 /
RDATA5 /
RDATA4 /
RDATA3 /
RDATA2 /
RDATA1 /
RDATA0 /
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
BPV7 /
BPV6 /
BPV5 /
BPV4 /
BPV3 /
BPV2 /
BPV1 /
BPV0 /
Signal
Name
RNEG7
RNEG6
RNEG5
RNEG4
RNEG3
RNEG2
RNEG1
RNEG0
RPOS7
RPOS6
RPOS5
RPOS4
RPOS3
RPOS2
RPOS1
RPOS0
QFP
141
105
Pin
112
142
104
111
69
76
34
41
70
77
33
40
4
5
PBGA
M12
M13
Ball
C12
A12
P12
C13
A13
P13
M3
M2
A3
C3
P3
A2
C2
P2
Signal
Type
DO
DO
Receive Negative Data Output 7:0.
This signal description applies to both RNEG and RPOS in
bipolar I/O mode. When the LXT384 Transceiver is in the:
When MCLK is provided with a clocking signal:
When MCLK is high:
When MCLK is low:
Note:
Receive Positive Data Output 7:0.
For the RPOS description, see RNEG.
Note:
• Host processor mode, during an LOS condition, AIS
• Hardware mode, RNEG and RPOS remain active
• The LXT384 Transceiver enters clock-recovery mode.
• A High signal on RNEG corresponds to receipt of a
• A High signal on RPOS corresponds to receipt of a
• These signals are valid on the falling or rising edges of
• The LXT384 Transceiver enters data recovery mode.
• These signals are valid on the falling or rising edges of
• RNEG and RPOS can be placed in a high-impedance
can be inserted into the receive path. See the
description of the GCR register RAISEN bit, in
Section 6.3.6, Receive Alarm Indication Signal (RAIS)
Enable.
during an LOS condition.
RNEG[7:0] act as active-high bipolar Non Return to
Zero (NRZ) receive signal outputs.
negative pulse on RTIP/RRING.
positive pulse on RTIP/RRING.
RCLK, depending on the CLKE input. See the CLKE pin
description in
Signals.
RNEG[7:0] act as RZ data receiver outputs.
RCLK, depending on the CLKE input. See the CLKE pin
description in
Signals.
tristate with the MCLK pin. (For details, see MCLK in
Section 5.5, Clocks and Clock-Related
For pin functions involving unipolar mode, see the
BPV pin description.
For pin functions involving unipolar mode, see the
RDATA pin description.
TM
TM
Table 10, Clocks and Clock-Related
Table 10, Clocks and Clock-Related
Signal Description
5.3 Framer/Mapper Signals
Signals.)
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