WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 57

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Figure 7
Cortina Systems
RNEGi
RPOSi
TNEGi
TPOSi
RCLKi
TCLKi
MCLK
JASEL0-1
Jitter Attenuator
When the LXT384 Transceiver is in the:
For information on jitter attenuation as it applies specifically to the receiver, see
Jitter
Standard E1 jitter-attenuation recommendations and specifications that the
LXT384 Transceiver JA meets are the following. (For more recommendations and
specifications, see
®
• Host Processor mode:
• Hardware mode:
• European Telecommunications Standards Institute (ETSI) publication, ETSI CTR12/13
• International Telecommunication Union (ITU) publications:
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
— The Global Control Register (GCR,
— Depending on the GCR register FIFO64 bit setting, the depth of the FIFO used in
— The low-limit jitter attenuator corner frequency depends on the FIFO depth and the
— The JASEL pin determines whether JA is positioned in the receive or transmit path.
— The FIFO length is fixed to 64 bits.
— The low-limit jitter attenuator corner frequency is fixed to 3.5 Hz for E1 mode, or
Attenuation.
is positioned in the receive or transmit path.
the JA is either a 32 x 2-bit FIFO or a 64 x 2-bit FIFO. (For FIFO64 bit details, see
Table 42
JACF bit setting in the GCR register. (For JACF bit details, see
Section 8.0,
6 Hz for T1 mode. (For more information on the JA corner frequency, see
in
Section 14.0, Jitter
x 32
in
Section 15.0, Recommendations and
Section 8.0,
Registers.)
IN CLK
IN
Clock Recovery Unit
Performance.)
Registers.)
FIFO
FIFO64
Table
OUT CLK
42) JASEL bits determine whether the JA
OUT
TM
TM
Specifications.)
I = inputs
o = outputs
6.6 Jitter Attenuation
Table 42
JASEL0-1
GCR control bits
Section 6.6,
in
Table 75
Page 57
TPOSo
RPOSo
TNEGo
RNEGo
TCLKo
RCLKo