WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 46

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
6.2
Note:
6.3
6.3.1
6.3.2
Cortina Systems
Initialization and Reset
Initialization for the LXT384 Transceiver occurs as follows:
For more information related to reset, see
Interface.
Receiver
The LXT384 Transceiver has eight identical receivers.
Receiver Clocking
In the receive mode, clocking for the LXT384 Transceiver receiver depends on the
following. When the LXT384 Transceiver is in:
For more information on data-recovery mode, see
Mode.
Receiver Inputs
A receiver processes input signals as follows:
®
1. During power-up, the LXT384 Transceiver is in an unknown state until the power supply
2. A write to the reset register (RES,
1. Through the line interface step-down transformer, typically from either a twisted-pair or
• Clock-recovery mode, the RCLK pin provides the recovered clock from the signal
• Clock-recovery mode with LOS conditions, at the RCLK output there is a transition from
• Data-recovery mode and MCLK is:
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
reaches approximately 60% of VCC. Also during power-up, an initial reset sets all
registers to their default values and resets the status and state machines for the LOS
detector circuit.
(Between 50 and 70% of VCC, the LXT384 Transceiver is in a critical zone. For more
information about this critical zone, see the application note on slow power-up rise time,
referenced in
all LXT384 Transceiver registers to their default values. When the reset cycle occurs:
a. In the Intel* processor non-multiplexed mode, the reset cycle is 2 microseconds
b. In all other modes, the reset cycle is 1 microsecond long.
received at RRING and RTIP.
RCLK (derived from recovered data) to MCLK. For more information on clock-recovery
mode, see
Receiver
— Low, the RCLK pin is in a high-impedance tristate.
— High, the RNEG and RPOS pins are internally connected to an EX-OR output to
a coaxial cable. (For transformer specifications, see
Interface-Unit Circuit
is sent to the receiver section of the LXT384 Transceiver.
long.
RCLK for external clock-recovery applications.
Clocking.
Section 6.3.3, Receiver Loss-Of-Signal Detector
Section 1.3, Related
Specifications.) After the transformer, the signal is terminated and
Table
Documents.)
Section 7.4.1, Host Processor Mode - Parallel
37) initiates a reset cycle that results in setting
Section 6.3.4, Receiver Data Recovery
TM
TM
Figure 6
and
and
6.2 Initialization and Reset
Section 6.3.1,
Section 12.0, Line-
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