WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 37

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Table 10
5.6
Cortina Systems
Clocks and Clock-Related Signals (Sheet 2 of 2)
Configuration and Mode-Select Signals
Table 11
For multi-function pins, the pin name in
®
1. DI: Digital Input
Signal
Name
MCLK
RCLK
SCLK
TCLK
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
lists and describes the LXT384 Transceiver configuration and mode-select signals.
QFP
Pin
10
PBGA
Ball
E1
Signal
Type
DI
Master Clock Input.
MCLK is an independent, free-running reference clock that must be
used at 1.544 MHz for T1 operation or 2.048 MHz for E1 operation, to
generate the following internal reference signals:
If MCLK is:
NOTE:
Caution: Whenever MCLK is not provided, the LXT384 Transceiver is
forced into a static state, possibly causing the TTIP/TRING outputs to
overheat. To prevent overheating, see
Receive Clock Output 7:0.
For information on RCLK, see
Shift Clock Input.
For information on SCLK, see
Interface
Transmit Clock Input 7:0.
For information on TCLK, see
• Reference clock during a blue-alarm transmit-all-ones condition.
• Generation of RCLK signal during a loss-of-signal condition.
• Timing reference for the integrated clock-recovery unit, and the
• Wait-state generation logic for host processors that use parallel
• Low continuously, the complete receive path is powered down and
• High continuously, the phase-locked loop clock-recovery circuit is
• MCLK is not required if the LXT384 Transceiver is used as an
• The TAOS generator uses MCLK as a timing reference. To ensure
• If MCLK is not provided, the LXT384 Transceiver cannot be used
integrated digital jitter attenuator.
interfaces.
output pins RCLK, RPOS, and RNEG are switched to a high-
impedance tristate.
disabled and the LXT384 Transceiver operates as only a simple
data receiver (without clock recovery).
analog front end without clock recovery and jitter attenuation.
the output frequency is within specification limits, MCLK must have
the applicable stability.
for data recovery with Motorola processors because wait states
cannot be added. (Wait-state generation through ACK is not
available.)
blue bold
Signals.
print indicates the signal being discussed.
Signal Description
TM
TM
5.3, Framer/Mapper
5.2, Microprocessor-Standard Bus and
5.3, Framer/Mapper
5.6 Configuration and Mode-Select
6.5, Line-Interface
Signals.
Signals.
Protection.
Page 37
Signals