WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 45

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
6.0
6.1
Note:
Cortina Systems
Functional Description
This functional description chapter follows the flow of signals through an
LXT384 Transceiver.
This chapter discusses the following topics:
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Functional Overview
The LXT384 Transceiver is a fully integrated octal line interface unit designed for T1
1.544 MBps and 2.048 MBps (E1) short-haul applications. (For a block diagram, see
Figure
The LXT384 Transceiver can be controlled either by a ‘Hardware mode’ that uses hard-
wired pins or by a ‘Host Processor mode’, which uses either a serial or parallel host
processor interface that is controlled in software. (For more information on selecting an
operating mode, see
Each transceiver front end interfaces with four lines: one pair of two lines for transmit, and
one pair of two lines for receive. These two pairs make up a digital data loop for full-duplex
transmission.
The TCLK pin provides the transmitter timing reference, and the MCLK pin provides the
receiver reference clock. The LXT384 Transceiver is designed to operate without any
reference clock when it is used as an analog front end (that is, for data recovery in the
receiver path and as a line driver in the transmit path). MCLK is mandatory if on-chip clock
recovery is required.
MCLK should be true to the recovered clock of the incoming data. It should be only
plesiochronous to MCLK.
All eight clock-recovery circuits share the same reference clock defined by the MCLK input
signal. (For details on MCLK, see
Signals.)
®
Section 6.1, Functional Overview
Section 6.2, Initialization and Reset
Section 6.3, Receiver
Section 6.4,
Section 6.5, Line-Interface Protection
Section 6.6, Jitter Attenuation
Section 6.7, Loopbacks
Section 6.8, Transmit All Ones Operations
Section 6.9, Performance Monitoring
Section 6.10, Hitless Protection Switching
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
1.)
Transmitter”
Table 2
in
Section 4.1, Operating Mode Multi-Function
Table 10
in
Section 5.5, Clocks and Clock-Related
TM
TM
6.0 Functional Description
Pins.)
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