WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 47

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
6.3.3
6.3.3.1
Cortina Systems
Receiver Loss-Of-Signal Detector
The LXT384 Transceiver loss-of-signal (LOS) detector circuit is designed to detect loss of
signals in both analog and digital domains. This circuit is independent of the data slicer.
The receiver monitor loads a digital counter at the RCLK frequency. The counter is
incremented each time a zero is received, and reset to zero each time a one (mark) is
received. Depending on the operation mode, a certain number of consecutive zeros sets the
LOS signal. The recovered clock is replaced by MCLK at the RCLK output with a minimum
amount of phase errors. MCLK is required for receive operation. When the LOS condition is
cleared, the LOS flag is reset and another transition replaces MCLK with the recovered
clock at RCLK. RPOS/RNEG will reflect the data content at the receiver input during the
entire LOS detection period for that channel.
G.755 and ETSI 300 233 - Loss of Signal Detection
®
2. The receiver inputs, RTIP (receives positive pulses) and RRING (receives negative
3. The peak detector samples a received signal and determines its maximum peak value.
4. The peak detector sends a percentage of the maximum peak value to the data slicers.
5. The data slicer processes the received signal, after which the signal simultaneously
• In hardware mode, it complies with the latest ITU G.775 (for E1) and ANSI T1.231 (for
• Under software control, the detector can be configured to comply to the ETSI ETS 300
• In G.775 mode a loss of signal is detected if the signal is below 200 mV (typical) for 32
• In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200 mV for
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
pulses), are processed through the internal differential amplifier. The differential
amplifier then sends the signal to the peak detector.
Recovered data is output at RPOS and RNEG in bipolar mode, or at RDATA in unipolar
mode. The recovered clock is output at RCLK. Use the CLKE pin to select the RPOS/
RNEG validation relative to the polarity of the edge of RCLK.
The receiver can:
— accurately recover signals in excess of 12 dB of attenuation
— receive signal levels well below 500 mV.
Regardless of received signal level, the peak detectors are held above a minimum level
of 0.150 V (typical), to provide immunity from impulsive noise.
This percentage acts as a threshold level to ensure an optimum signal-to-noise ratio.
The threshold level is typically 50% for E1 applications (see
applications (see
goes to both the clock and data-recovery sections.
— The data and timing recovery circuits provide an input jitter tolerance better than
— Depending on the options selected, recovered clock and data signals may be
T1) recommendations.
233 specification (
consecutive pulse intervals. The LOS flag is reset when the received signal reaches
12.5% ones density (4 marks in a sliding 32-bit period) with no more than 15
consecutive zeros and the signal level exceeds 250 mV (typical). Following the next
MCLK transition, MCLK is replaced with a recovered clock at the RCLK output.
2048 consecutive intervals (1 ms). The LOS condition is cleared and the output pin
required by ITU G.823, as shown in Test Specifications,
routed through the jitter attenuator, through the HDB3/AMI decoder, and may be
output to the framer as either bipolar or unipolar data.
Table
LACS
63).
Register).
TM
TM
Figure
Table
62) or 70% for T-1
33.
6.3 Receiver
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