WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 65

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Table 22
7.4
7.4.1
Table 23
Cortina Systems
LXT384 Transceiver Operation Mode Summary (Sheet 2 of 2)
Host Processor Modes
When the MODE pin is connected high, the following Host Processor modes are available.
Host Processor Mode - Parallel Interface
The parallel interface (listed in
is used to control configuration of the LXT384 Transceiver and to report the status of
various operations. The LXT384 Transceiver has a flexible, generic 8-bit parallel host
processor interface designed to support both non-multiplexed and multiplexed address/data
bus systems for both Motorola* bus and Intel* bus topologies.
interface modes that can be selected with the pins MODE, MOT/INTL, and MUX.
Host Processor Mode - Parallel Interface Selections
The Host Processor mode parallel interface includes an address bus (A4:0) and a data bus
(D7:0) for non-multiplexed operation and an 8-bit address/data bus for multiplexed
operation. The LXT384 Transceiver has a 5-bit address bus and provides 22 user-
accessible 8-bit registers for configuration, alarm monitoring, and control of the
LXT384 Transceiver.
Control signals that the LXT384 Transceiver and host processors have in common include
ACK/ RDY, ALE, CS, DS, INT, RD, R/W, and WR. An internal wait-state generator controls
the ACK/ RDY handshake output signal, which is compatible with both Motorola* and Intel*
processors.
When the processor interface selected is for a:
®
1. Hardware mode only.
MODE
High
High
High
High
MCLK
•
•
• Motorola* processor and ACK is low, then during a:
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
H
H
H
H
H
H
H
Section 7.4.1, Host Processor Mode - Parallel Interface
Section 7.4.2, Host Processor Mode - Serial Interface
— Read cycle, ACK indicates that valid information is on the data bus.
MOT/
Clocked
Clocked
INTL
High
High
Low
Low
TCLK
H
H
H
L
L
LOOP
MUX
High
High
Low
Low
Open
Open
H
H
L
L
L
1
Host Processor mode, Motorola* processor parallel interface, non-multiplexed
Host Processor mode, Motorola* processor parallel interface, multiplexed
Host Processor mode, Intel* processor parallel interface, non-multiplexed
Host Processor mode, Intel* processor parallel interface, multiplexed
Table 2
Receive Mode
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Data Recovery
in
Section 4.1, Operating Mode Multi-Function
Pulse Shaping OFF
Pulse Shaping OFF
Pulse Shaping OFF
Pulse Shaping OFF
Pulse Shaping OFF
Pulse Shaping ON
Interface Selected
Transmit Mode
Power down
TM
TM
Table 23
7.4 Host Processor Modes
Remote Loopback
Remote Loopback
Remote Loopback
Analog Loopback
Analog Loopback
lists the four parallel
No Loopback
No Loopback
Loopback
Page 65
Pins)